US2024020093A1PendingUtilityA1

Compute-in-memory support for different data formats

Assignee: INTEL CORPPriority: Sep 29, 2023Filed: Sep 29, 2023Published: Jan 18, 2024
Est. expirySep 29, 2043(~17.2 yrs left)· nominal 20-yr term from priority
G06F 7/483
50
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Systems, apparatuses and methods include technology that identifies workload numbers associated with a workload. The technology converts the workload numbers to block floating point numbers based on a division of mantissas of the workload numbers into sub-words and executes a compute-in memory operation based on the sub-words to generate partial products.

Claims

exact text as granted — not AI-modified
We claim: 
     
         1 . A computing system comprising:
 a compute-in-memory array to execute computations and store data associated with a workload; and   logic coupled to one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:   identify workload numbers associated with the workload,   convert the workload numbers to block floating point numbers based on a division of mantissas of the workload numbers into sub-words, and   execute a compute-in memory operation based on the sub-words to generate partial products.   
     
     
         2 . The computing system of  claim 1 , wherein to convert the workload numbers to block floating point numbers, the logic coupled to the one or more substrates is to:
 append sign bits of the workload numbers to the sub-words.   
     
     
         3 . The computing system of  claim 1 , wherein to convert the workload numbers to block floating point numbers, the logic coupled to the one or more substrates is to:
 identify a maximum exponent value from exponents of the workload numbers;   identify a lower exponent value from the exponents that is smaller than the maximum exponent value; and   identify an adjustment to the lower exponent value to adjust the lower exponent value to be equal to the maximum exponent value.   
     
     
         4 . The computing system of  claim 3 , wherein to identify the adjustment to the lower exponent value, the logic coupled to the one or more substrates is to:
 subtract the lower exponent value from the maximum exponent value to identify a difference.   
     
     
         5 . The computing system of  claim 4 , wherein to convert the workload numbers to block floating point numbers, the logic coupled to the one or more substrates is to:
 identify a lower mantissa from the mantissas that is associated with the lower exponent value; and   right shift the lower mantissa based on the difference.   
     
     
         6 . The computing system of  claim 3 , wherein the logic coupled to the one or more substrates is to:
 accumulate the partial products to generate an accumulated mantissa;   renormalize the accumulated mantissa to generate a final mantissa by a left-shift of the accumulated mantissa a number of times until a largest magnitude bit of the accumulated mantissa has a predetermined value;   determine a final exponent based on an exponent value associated with the partial products, the maximum exponent value and the number of times; and   associate the final exponent with the final mantissa to generate a final output.   
     
     
         7 . The computing system of  claim 1 , wherein the partial products include a first partial product and a second partial product,
 wherein the logic coupled to the one or more substrates is to:   accumulate a most significant bit of the first partial product with a least significant bit of the second partial product during accumulation of the first partial product and the second partial product,   wherein the workload numbers include extended fixed-point numbers or floating point numbers.   
     
     
         8 . A semiconductor apparatus comprising:
 one or more substrates; and   logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:   identify workload numbers associated with a workload,   convert the workload numbers to block floating point numbers based on a division of mantissas of the workload numbers into sub-words, and   execute a compute-in memory operation based on the sub-words to generate partial products.   
     
     
         9 . The apparatus of  claim 8 , wherein to convert the workload numbers to block floating point numbers, the logic coupled to the one or more substrates is to:
 append sign bits of the workload numbers to the sub-words.   
     
     
         10 . The apparatus of  claim 8 , wherein to convert the workload numbers to block floating point numbers, the logic coupled to the one or more substrates is to:
 identify a maximum exponent value from exponents of the workload numbers;   identify a lower exponent value from the exponents that is smaller than the maximum exponent value; and   identify an adjustment to the lower exponent value to adjust the lower exponent value to be equal to the maximum exponent value.   
     
     
         11 . The apparatus of  claim 10 , wherein to identify the adjustment to the lower exponent value, the logic coupled to the one or more substrates is to:
 subtract the lower exponent value from the maximum exponent value to identify a difference.   
     
     
         12 . The apparatus of  claim 11 , wherein to convert the workload numbers to block floating point numbers, the logic coupled to the one or more substrates is to:
 identify a lower mantissa from the mantissas that is associated with the lower exponent value; and   right shift the lower mantissa based on the difference.   
     
     
         13 . The apparatus of  claim 10 , wherein the logic coupled to the one or more substrates is to:
 accumulate the partial products to generate an accumulated mantissa;   renormalize the accumulated mantissa to generate a final mantissa by a left-shift of the accumulated mantissa a number of times until a largest magnitude bit of the accumulated mantissa has a predetermined value;   determine a final exponent based on an exponent value associated with the partial products, the maximum exponent value and the number of times; and   associate the final exponent with the final mantissa to generate a final output.   
     
     
         14 . The apparatus of  claim 8 , wherein the partial products include a first partial product and a second partial product,
 wherein the logic coupled to the one or more substrates is to:   accumulate a most significant bit of the first partial product with a least significant bit of the second partial product during accumulation of the first partial product and the second partial product,   wherein the workload numbers include extended fixed-point numbers or floating point numbers.   
     
     
         15 . The apparatus of  claim 8 , wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates. 
     
     
         16 . A method comprising:
 identifying workload numbers associated with a workload;   converting the workload numbers to block floating point numbers based on a division of mantissas of the workload numbers into sub-words; and   executing a compute-in memory operation based on the sub-words to generate partial products.   
     
     
         17 . The method of  claim 16 , wherein the converting the workload numbers to block floating point numbers comprises:
 appending sign bits of the workload numbers to the sub-words.   
     
     
         18 . The method of  claim 16 , wherein the converting the workload numbers to block floating point numbers comprises:
 identifying a maximum exponent value from exponents of the workload numbers;   identifying a lower exponent value from the exponents that is smaller than the maximum exponent value; and   identifying an adjustment to the lower exponent value to adjust the lower exponent value to be equal to the maximum exponent value.   
     
     
         19 . The method of  claim 18 ,
 wherein the identifying the adjustment to the lower exponent value, includes subtracting the lower exponent value from the maximum exponent value to identify a difference; and   wherein the converting the workload numbers to block floating point numbers comprises:
 identifying a lower mantissa from the mantissas that is associated with the lower exponent value, and 
 right shifting the lower mantissa based on the difference. 
   
     
     
         20 . The method of  claim 18 , wherein the partial products include a first partial product and a second partial product, and further wherein the method further comprises:
 accumulating the partial products to generate an accumulated mantissa;   renormalizing the accumulated mantissa to generate a final mantissa by a left-shift of the accumulated mantissa a number of times until a largest magnitude bit of the accumulated mantissa has a predetermined value;   determining a final exponent based on an exponent value associated with the partial products, the maximum exponent value and the number of times;   associating the final exponent with the final mantissa to generate a final output; and   accumulating a most significant bit of the first partial product with a least significant bit of the second partial product during accumulation of the first partial product and the second partial product,   wherein the workload numbers include extended fixed-point numbers or floating point numbers.

Join the waitlist — get patent alerts

Track US2024020093A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.