Memory system including a memory controller

Abstract

A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.

What is claimed is: 
     
         1 . A memory module, comprising:
 a pool of first memory;   a pool of second memory;   a registering clock driver coupled to the pool of first memory and the pool of second memory; and   an interface coupled to the registering clock driver,   wherein the registering clock driver is selectively connected to at least one among the pool of first memory and the pool of second memory.   
     
     
         2 . The memory module of  claim 1 , wherein the interface is selectively connected to one of the pool of first memory and the pool of second volatile memory through the registering clock driver for transmitting at least one of a command signal, an address signal, or a clock signal to a connected pool. 
     
     
         3 . The memory module of  claim 1 , wherein the interface is connected to a channel including at least two sub-channels,
 wherein each sub-channel operates independently,   wherein a command signal or an address signal is transferred independently on the two sub-channels at the same time, and   wherein each sub-channel comprises a group of signal lines for the command signal and the address signal.   
     
     
         4 . The memory module of  claim 1 , wherein the interface is configured through selective connection to reduce loads in an operation of transferring signals between the memory module and an external device and improve a quality of transferred signals. 
     
     
         5 . The memory module of  claim 1 , wherein the registering clock driver is configured to transfer at least one of a command signal, an address signal, or a clock signal, which is input from an external device, into either the pool of first memory, the pool of second memory, or both the pools of first and second memories. 
     
     
         6 . The memory module of  claim 1 , wherein the registering clock driver is configured to selectively transfer at least one of a command signal or an address signal into either the pool of first memory or the pool of second memory while transferring a clock signal to both the pool of first and second memories. 
     
     
         7 . The memory module of  claim 1 , further comprising:
 a buffer chip configured to transfer data between an external device and the one of the pool of first memory and the pool of second memory;   a controller configured to selectively activate at least one among a first path for connecting the interface to the pool of first memory and a second path for connecting the interface to the pool of the second memory.   
     
     
         8 . A memory module, comprising:
 a first memory chip; and   a second memory chip coupled to an external device through a channel,   wherein the channel operably couples to the second memory chip, not the first memory chip.   
     
     
         9 . The memory module of  claim 8 , further comprising:
 a buffer chip configured to buffer data transferred between the second memory chip and the external device;   a registering clock driver coupled to the first memory chip and the second memory chip; and   an interface coupled to the registering clock driver, and   wherein the registering clock driver is selectively connected to either the first memory chip, the second memory chip, or both the first and second memory chips to transfer at least one of a command signal, an address signal, or a clock signal which is input from an external device.   
     
     
         10 . The memory module of  claim 8 , wherein the interface is connected to a channel including at least two sub-channels,
 wherein each sub-channel operates independently,   wherein the command signal or the address signal is transferred independently on the two sub-channels at the same time,   wherein each sub-channel comprises a group of signal lines for the command signal and the address signal, and   wherein the interface is selectively connected to either the first memory chip, the second memory chip, or both the first and second memory chips through the registering clock driver for selectively transmitting the command signal or the address signal to either the first memory chip or the second memory chip while transferring the clock signal to both the first and second memory chips.   
     
     
         11 . The memory module of  claim 8 , wherein, while the channel is operably coupled to the second memory chip, a path between the channel and the first memory chip is activated. 
     
     
         12 . The memory module of  claim 8 , wherein the channel is operably coupled to the second memory chip, not the first memory chip, during a preset time. 
     
     
         13 . The memory module of  claim 8 , wherein the channel is operably coupled to the second memory chip, not the first memory chip, to reduce loads in an operation of transferring signals between the memory module and an external device and improve a quality of transferred signals. 
     
     
         14 . A DRAM memory module in which a memory controller is applicable to transmit data to another memory module with a channel with full capacity comprising two group of signal lines, comprising:
 a first DRAM memory chip group configured to transfer a first data through a first portion of the channel, the first portion comprising a first group of signal lines;   a second DRAM memory chip group configured to transfer a second data through a second portion of the channel, the second portion comprising a second group of signal lines; and   wherein the DRAM memory module transmits either the first data stored at the first DRAM memory chip group, the second data stored at the second DRAM memory chip, or both the first data and the second data at a time.   
     
     
         15 . The memory module of  claim 14 , wherein the channel including two sub-channels, each channel corresponding to the each group of signal line,
 wherein each sub-channel operates independently,   wherein the command signal or the address signal is transferred independently on the two sub-channels at the same time,   wherein each sub-channel comprises a group of signal lines for the command signal and the address signal, and   wherein the memory controller is selectively connected to either the first memory chip, the second memory chip, or both the first and second memory chips for selectively transmitting the command signal or the address signal to either the first memory chip or the second memory chip while the clock signal is commonly connected to both the first and second memory chips.   
     
     
         16 . The DRAM memory module according to  claim 14 , wherein the DRAM memory module allows asynchronous transmission of the first data and the second data. 
     
     
         17 . The DRAM memory module according to  claim 14 , wherein the memory controller asynchronously transmits the first data and the second data to the first DRAM memory chip group and the second DRAM memory chip group. 
     
     
         18 . The DRAM memory module according to  claim 14 , further comprising a registering clock driver configured to transfer a first command signal, a first address signal and a first clock signal to the first DRAM memory chip group and to transfer a second command signal, a second address signal and a second clock signal to the second DRAM memory chip group. 
     
     
         19 . The DRAM memory module according to  claim 14 , wherein the second data transmitted through the second group of signal lines is transferred non-simultaneously from the first data transmitted through the first group of the signal lines. 
     
     
         20 . The DRAM memory module according to  claim 14 , wherein after the first memory chip group receives the first command signal, the first address signal and the first clock signal, the second memory chip group receives a second command signal, a second address signal and a second clock signal. 
     
     
         21 . The DRAM memory module according to  claim 14 , wherein when the first memory chip group receives the first command signal, the first address signal, and the first clock signal, the second memory chip group concurrently receives a second command signal, a second address signal and a second clock signal. 
     
     
         22 . The DRAM memory module according to  claim 14 , wherein the first and second memory chip groups each transfer the first and second data through each part of signal lines in the channel regardless of a status indicating whether the other memory chip transfer data, and
 wherein the channel comprising at least two sub-channels including a group of signal lines for a command signal and an address signal.   
     
     
         23 . The DRAM memory module according to  claim 14 , wherein both the first portion of the channel and the second portion of the channel are electrically connected to a module interface of the another memory module. 
     
     
         24 . The DRAM memory module according to  claim 14 , wherein signal lines for transmitting the first data and signal lines for transmitting the second data are disposed in parallel. 
     
     
         25 . The DRAM memory module according to  claim 14 , wherein signal lines for transmitting the first data and signal lines for transmitting the second data are disposed along same row direction. 
     
     
         26 . The DRAM memory module according to  claim 14 , wherein the first data and the second data are transferred independently. 
     
     
         27 . The DRAM memory module according to  claim 14 , wherein signal lines for transmitting the first data and signal lines for transmitting the second data are disposed alternately with each other. 
     
     
         28 . The DRAM memory module according to  claim 14 , wherein the first group of signal lines is dedicated to the first DRAM memory chip group and the second group of signal lines is dedicated to the second DRAM memory chip group. 
     
     
         29 . The DRAM memory module according to  claim 14 , further comprising an interface coupled to the memory controller. 
     
     
         30 . The DRAM memory module according to  claim 29 , wherein the interface includes the first group of signal lines and the second group of signal lines, and the interface is operatable when one of the first and second group of signal lines is activated. 
     
     
         31 . The DRAM memory module according to  claim 29 , wherein the first command signals and first address signals for the first DRAM memory chip group and the second command signals and second address signals for the second DRAM memory chip group are transferred through the interface from the memory controller. 
     
     
         32 . The DRAM memory module according to  claim 29 , wherein the first data and the second data are transferred through the interface between the DRAM memory module and the memory controller. 
     
     
         33 . The DRAM memory module according to  claim 14 , wherein the controller is selectively connected to one of the first DRAM memory chip group and the second DRAM memory chip group to reduce loads in an operation of transferring signals between the memory module and an external device and improve a quality of transferred signals. 
     
     
         34 . The DRAM memory module according to  claim 18 , wherein the first clock signal transferred to the first DRAM memory chip group and the second clock signal transferred to the second DRAM memory chip group are same as each other.