US2024008298A1PendingUtilityA1

Light emitting diode display with redundancy scheme

Assignee: APPLE INCPriority: Mar 15, 2013Filed: Aug 17, 2023Published: Jan 4, 2024
Est. expiryMar 15, 2033(~6.6 yrs left)· nominal 20-yr term from priority
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Claims

Abstract

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 - 17 . (canceled) 
     
     
         18 . A display panel comprising:
 a substrate;   a group of bottom electrodes on the substrate;   a bank layer over the substrate;   a group of bank openings in the bank layer, each bank opening including a corresponding bottom electrode;   a group of vertical light emitting diode (LED) devices bonded to the group of bottom electrodes with a corresponding group of solder bonding layers.   
     
     
         19 . The display panel of  claim 18 , wherein each vertical light emitting diode device in the group of vertical light emitting diode devices includes a micro p-n diode. 
     
     
         20 . The display panel of  claim 19 , wherein each vertical light emitting diode device in the group of vertical light emitting diode devices has a maximum width of 1 μm-100 μm. 
     
     
         21 . The display panel of  claim 20 , wherein each micro p-n diode has a maximum width of 1 μm-5 μm. 
     
     
         22 . The display panel of  claim 20 , wherein each micro p-n diode has a maximum thickness of 5 μm or less. 
     
     
         23 . The display panel of  claim 20 , wherein no vertical light emitting diode device of the group of vertical light emitting diode devices spans along a sidewall of a corresponding bank opening. 
     
     
         24 . The display panel of  claim 20 , further comprising a passivation layer formed around sidewalls of the group of vertical light emitting diodes devices. 
     
     
         25 . The display panel of  claim 20 , further comprising a top electrode layer spanning over and in electrical contact with the group of vertical light emitting diode devices. 
     
     
         26 . The display panel of  claim 25 , further comprising an opening though the bank layer, wherein the top conductive contact layer is electrically connected with a ground tie line through the via opening. 
     
     
         27 . The display panel of  claim 25 , further comprising ground tie line over the bank layer, wherein the top electrode layer is electrically connected with the ground tie line. 
     
     
         28 . The display panel of  claim 25 , wherein each bottom electrode of the group of bottom electrode layers is reflective to the visible wavelength range of 380 nm-750 nm. 
     
     
         29 . The display panel of  claim 28 , wherein each bottom electrode includes a multiple-layer stack. 
     
     
         30 . The display panel of  claim 29 , wherein the multiple-layer stack includes a metallic layer selected from the group consisting of silver, aluminum, and titanium. 
     
     
         31 . The display panel of  claim 20 , wherein each bottom electrode spans along sidewalls of a corresponding bank opening. 
     
     
         32 . The display panel of  claim 31 , wherein each bottom electrode includes a multiple-layer stack. 
     
     
         33 . The display panel of  claim 32 , wherein the multiple-layer stack includes a metallic layer selected from the group consisting of silver, aluminum, and titanium. 
     
     
         34 . The display panel of  claim 18 , wherein each bottom electrode is coupled to a corresponding driving transistor. 
     
     
         35 . The display panel of  claim 18 , wherein the group of vertical LED devices is arranged within a group of subpixels, each subpixel including a redundant pair of vertical LED devices.

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