Semiconductor device with robust inner spacer

Abstract

A semiconductor structure includes a plurality of semiconductor layers vertically stacked over a semiconductor substrate. Each of the plurality of semiconductor layers defining a channel region of the semiconductor structure. A source/drain region is located on opposite ends of the plurality of semiconductor layers while a metal gate stack surrounds each of the plurality of semiconductor layers. An inner spacer having a concave surface curving inward in a direction towards the source/drain region is located between each of the plurality of semiconductor layers for separating the metal gate stack from the source/drain region.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a plurality of semiconductor layers vertically stacked over a semiconductor substrate, each of the plurality of semiconductor layers defining a channel region of the semiconductor structure;   a source/drain region located on opposite ends of the plurality of semiconductor layers;   a metal gate stack surrounding each of the plurality of semiconductor layers; and   an inner spacer located between each of the plurality of semiconductor layers, the inner spacer having a concave surface curving inward in a direction towards the source/drain region, the inner spacer separating the metal gate stack from the source/drain region.   
     
     
         2 . The semiconductor structure of  claim 1 , further comprising:
 a sidewall spacer located along opposite sidewalls of the metal gate stack, wherein a second surface of the inner spacer is in contact with the sidewall spacer.   
     
     
         3 . The semiconductor structure of  claim 1 , wherein the inner spacer having the concave surface comprises opposite outer portions of the inner spacer being wider than a middle portion of the inner spacer. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the inner spacer has a shape that includes two opposite segments and a vertical segment, the two opposite segments being connected by the vertical segment in the shape of a letter “C”, the two opposite segments having a width that is larger than a width of the vertical segment. 
     
     
         5 . The semiconductor structure of  claim 1 , further comprises:
 a portion of the semiconductor substrate below the plurality of semiconductor layers being located between shallow trench isolation regions.   
     
     
         6 . The semiconductor structure of  claim 1 , wherein the concave surface of the inner spacer is relative to an outer surface of the metal gate stack for providing an uniform thickness to the inner spacer and protecting the source/drain region, wherein edges of the plurality of semiconductor layers have a substantially square shape. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein the plurality of semiconductor layers comprises at least one of a nanosheet, a nanowire, and a nano-ellipse. 
     
     
         8 . A method of forming a semiconductor structure, comprising:
 forming a plurality of semiconductor layers vertically stacked over a semiconductor substrate, each of the plurality of semiconductor layers defining a channel region of the semiconductor structure;   forming a source/drain region located on opposite ends of the plurality of semiconductor layers;   forming a metal gate stack surrounding each of the plurality of semiconductor layers; and   forming an inner spacer located between each of the plurality of semiconductor layers, the inner spacer having a concave surface curving inward in a direction towards the source/drain region, the inner spacer separating the metal gate stack from the source/drain region.   
     
     
         9 . The method of  claim 8 , wherein the inner spacer having the concave surface comprises opposite outer portions of the inner spacer being wider than a middle portion of the inner spacer. 
     
     
         10 . The method of  claim 8 , wherein the inner spacer has a shape that includes two opposite segments and a vertical segment, the two opposite segments being connected by the vertical segment in the shape of a letter “C”, the two opposite segments having a width that is larger than a width of the vertical segment. 
     
     
         11 . The method of  claim 8 , wherein the concave surface of the inner spacer is relative to an outer surface of the metal gate stack for providing an uniform thickness to the inner spacer and protecting the source/drain region, wherein edges of the plurality of semiconductor layers have a substantially square shape. 
     
     
         12 . The method of  claim 8 , wherein the plurality of semiconductor layers comprises at least one of a nanosheet, a nanowire, and a nano-ellipse. 
     
     
         13 . The method of  claim 8 , further comprising:
 forming a nanosheet stack on the substrate, the nanosheet stack comprising an alternating sequence of sacrificial semiconductor layers and semiconductor channel layers;   patterning the nanosheet stack to form a nanosheet fin; and   forming a dummy gate on the nanosheet fin.   
     
     
         14 . The method of  claim 13 , further comprising:
 etching outer portions of the sacrificial semiconductor layers, wherein etching the outer portions of the sacrificial semiconductor layers forms a first indentation region; and   deposition sacrificial dielectric layer within the first indentation region.   
     
     
         15 . The method of  claim 14 , wherein the sacrificial dielectric layer has good etch selectivity to the sacrificial semiconductor layers and includes at least one of SiO 2 , SiBCN, SiCN, SiOCN, Ge, and SiGe. 
     
     
         16 . The method of  claim 15 , further comprising:
 conformally depositing a spacer material to form a sidewall spacer along opposite sidewalls of the dummy gate; and   using the sidewall spacer along sidewalls of the dummy gate as a mask, etching the nanosheet fin in a way such that a remaining portion of the nanosheet fin is vertically aligned with the sidewall spacer.   
     
     
         17 . The method of  claim 14 , further comprising:
 removing the sacrificial dielectric material; and   etching the outer portions of the sacrificial semiconductor layers, wherein etching the outer portions of the sacrificial semiconductor layers forms a second indentation region.   
     
     
         18 . The method of  claim 16 , further comprising:
 forming the inner spacer on opposite sides of the sacrificial semiconductor layers;   epitaxially growing the source/drain regions; and   forming a dielectric layer above the source/drain regions and between portions of the sidewall spacer being adjacent to the source/drain regions.   
     
     
         19 . The method of  claim 18 , further comprising:
 removing the dummy gate, wherein removing the dummy gate creates a recess between the sidewall spacer; and   selectively removing the sacrificial semiconductor layers.   
     
     
         20 . The method of  claim 19 , further comprising:
 forming the metal gate stack within the recess, the metal gate stack surrounding the plurality of semiconductor layers and being separated from the source/drain regions by the inner spacer.