Method for semiconductor die edge protection and semiconductor die separation

Abstract

Methods for protecting edges of semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, a plurality of trenches may be formed on a front side of a substrate including a plurality of semiconductor dies. Individual trenches may correspond to scribe lines of the substrate where each trench includes a depth greater than a final thickness of the semiconductor dies. A dielectric layer may be formed on sidewalls of the trenches, thereby protecting the edges of the semiconductor dies, prior to filling the trenches with an adhesive material. Subsequently, the substrate may be thinned from a back side such that the adhesive material in the trenches may be exposed from the back side. The adhesive material may be removed to singulate individual semiconductor dies of the plurality from the substrate.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 an integrated circuit formed on a front side of a semiconductor substrate;   a first dielectric layer on a sidewall of the semiconductor substrate; and   a second dielectric layer on a back side of the semiconductor substrate opposite to the front side, the second dielectric layer discontinuous from the first dielectric layer.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first dielectric layer includes at least two dielectric materials. 
     
     
         3 . The semiconductor device of  claim 1 , wherein:
 the first dielectric layer includes a first dielectric material; and   the second dielectric layer includes a second dielectric material different from the first dielectric material.   
     
     
         4 . The semiconductor device of  claim 3 , wherein the first and second dielectric materials include an oxide, a nitride, an oxynitride, or a combination thereof. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising:
 one or more vias extending from the front side of the semiconductor substrate past the second dielectric material on the back side, the one or more vias coupled with the integrated circuit and configured to provide one or more electrical connections for the integrated circuit on a surface of the second dielectric material.   
     
     
         6 . The semiconductor device of  claim 1 , wherein the first and second dielectric layers share an interface vertically aligned with the sidewall of the semicondutor device. 
     
     
         7 . A semiconductor device, comprising:
 an integrated circuit formed on a front side of a semiconductor substrate;   a first dielectric layer on a back side of the semiconductor substrate opposite to the front side; and   a second dielectric layer on a sidewall of the semiconductor substrate and directly contacting the first dielectric layer at a substantially vertical interface coplanar with the sidewall of the semiconductor device.   
     
     
         8 . The semiconductor device of  claim 7 , wherein the second dielectric layer is discontinuous from the first dielectric layer. 
     
     
         9 . The semiconductor device of  claim 7 , wherein the second dielectric layer includes at least two dielectric materials. 
     
     
         10 . The semiconductor device of  claim 7 , wherein:
 the first dielectric layer includes a first dielectric material; and   the second dielectric layer includes a second dielectric material different from the first dielectric material.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the first and second dielectric materials include an oxide, a nitride, an oxynitride, or a combination thereof. 
     
     
         12 . The semiconductor device of  claim 7 , further comprising:
 one or more vias extending from the front side of the semiconductor substrate past the second dielectric material on the back side, the one or more vias coupled with the integrated circuit and configured to provide one or more electrical connections for the integrated circuit on a surface of the second dielectric material.