Shadow caches for level 2 cache controller

Abstract

An apparatus including a CPU core and a L1 cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives an indication from the L1 controller that a cache line A is being relocated from the L1 main cache to the L1 victim cache; in response to the indication, update the shadow L1 main cache to reflect that the cache line A is no longer located in the L1 main cache; and in response to the indication, update the shadow L1 victim cache to reflect that the cache line A is located in the L1 victim cache.

What is claimed is: 
     
         1 . A circuit device comprising:
 a processor core;   a first cache subsystem that includes:
 a first cache memory configured to store a first set of cache entries; 
 a second cache memory configured to store a second set of cache entries; and 
 a first cache controller coupled to the processor core, the first cache memory and the second cache memory, wherein the first cache controller is configured to evict a cache entry from the first cache memory by storing the cache entry in the second cache memory; and 
   a second cache subsystem that includes:
 a first tag memory associated with the first cache memory and configured to store a first set of tag data associated with the first set of cache entries; 
 a second tag memory associated with the second cache memory and configured to store a second set of tag data associated with the second set of cache entries; and 
 a second cache controller coupled to the first cache controller, the first tag memory, and the second tag memory. 
   
     
     
         2 . The circuit device of  claim 1 , wherein:
 the eviction of the cache entry from the first cache memory by the first cache controller includes providing an indication of the eviction to the second cache controller; and   wherein the second cache controller is configured to modify the first set of tag data and the second set of tag data based on the indication.   
     
     
         3 . The circuit device of  claim 2 , wherein:
 the cache entry is a first cache entry;   the first cache controller is configured to provide, to the second cache controller, a request for data associated with a second cache entry;   the eviction of the cache entry from the first cache memory is in response to receiving the data associated with the second cache entry; and   the request for the data associated with the second cache entry includes the indication of the eviction of the first cache entry from the first cache memory.   
     
     
         4 . The circuit device of  claim 1 , wherein the second cache controller is configured to:
 receive a request to read data;   determine whether the request corresponds to a hit or a miss in the first cache memory using the first tag memory; and   based on the request corresponding to a hit in the first cache memory, provide a snoop request for the data to the first cache controller.   
     
     
         5 . The circuit device of  claim 4 , wherein:
 the second cache subsystem includes a third cache memory; and   the second cache controller is further configured to, based on the request corresponding to a miss in the first cache memory:
 determine whether the request corresponds to a hit or a miss in the third cache memory; and 
 based on the request corresponding to a hit in the third cache memory, provide the data using the third cache memory. 
   
     
     
         6 . The circuit device of  claim 1 , wherein the second cache controller is configured to:
 receive a request to write a first set of data;   determine whether the request corresponds to a hit or a miss in the first cache memory using the first tag memory; and   based on the request corresponding to a hit in the first cache memory, provide a snoop read and invalidate request to the first cache controller.   
     
     
         7 . The circuit device of  claim 6 , wherein the second cache controller is further configured to, based on the snoop read and invalidate request returning a second set of data indicated as modified:
 merge the first set of data and the second set of data to produce a merged set of data; and   cause the merged set of data to be written.   
     
     
         8 . The circuit device of  claim 7 , wherein the second cache controller is further configured to, based on the snoop read and invalidate request returning the second set of data indicated as unmodified, cause the first set of data to be written. 
     
     
         9 . The circuit device of  claim 1 , wherein the first set of tag data and the second set of tag data include address data and coherence data. 
     
     
         10 . The circuit device of  claim 1 , wherein:
 the first cache subsystem is a level-one (L1) cache subsystem; and   the second cache subsystem is a level-two (L2) cache subsystem.   
     
     
         11 . The circuit device of  claim 1 , wherein the first cache memory and the second cache memory have different associativity. 
     
     
         12 . The circuit device of  claim 1 , wherein:
 the first cache subsystem includes a set of buffers configured to store a third set of cache entries for transfer to the second cache subsystem; and   second tag memory is configured to store a third set of tag data associated with the third set of cache entries.   
     
     
         13 . A circuit device comprising:
 a first cache subsystem that includes:
 a first tag memory associated with a first cache memory of a second cache subsystem and configured to store a first set of tag data associated with the first cache memory; 
 a second tag memory associated with a second cache memory of the second cache subsystem and configured to store a second set of tag data associated with the second cache memory; and 
 a cache controller coupled to the first tag memory, the second tag memory, and the second cache subsystem, wherein the cache controller is configured to modify the first set of tag data and the second set of tag data based on a cache entry being evicted from the first cache memory and stored in the second cache memory. 
   
     
     
         14 . The circuit device of  claim 13 , wherein:
 the cache entry is a first cache entry;   the cache controller is configured to receive, from the second cache subsystem, a request for data associated with a second cache entry to replace the first cache entry in the first cache memory; and   the request for the data associated with the second cache entry includes an indication of the eviction of the first cache entry from the first cache memory. The circuit device of  claim 13 , wherein the cache controller is configured to:   receive a request to read data;   determine whether the request corresponds to a hit or a miss in the first cache memory using the first tag memory; and   based on the request corresponding to a hit in the first cache memory, provide a snoop request for the data to the second cache subsystem.   
     
     
         16 . The circuit device of claim  15 , wherein:
 the first cache subsystem includes a third cache memory; and   the cache controller is further configured to, based on the request corresponding to a miss in the first cache memory:
 determine whether the request corresponds to a hit or a miss in the third cache memory; and 
 based on the request corresponding to a hit in the third cache memory, provide the data using the third cache memory. 
   
     
     
         17 . The circuit device of  claim 13 , wherein the cache controller is configured to:
 receive a request to write a first set of data;   determine whether the request corresponds to a hit or a miss in the first cache memory using the first tag memory; and   based on the request corresponding to a hit in the first cache memory, provide a snoop read and invalidate request to the second cache subsystem.   
     
     
         18 . The circuit device of  claim 17 , wherein the cache controller is further configured to, based on the snoop read and invalidate request returning a second set of data indicated as modified:
 merge the first set of data and the second set of data to produce a merged set of data; and   cause the merged set of data to be written.   
     
     
         19 . The circuit device of  claim 18 , wherein the cache controller is further configured to, based on the snoop read and invalidate request returning the second set of data indicated as unmodified, cause the first set of data to be written. 
     
     
         20 . The circuit device of  claim 13 , wherein the first set of tag data and the second set of tag data include address data and coherence data. 
     
     
         21 . The circuit device of  claim 13 , wherein:
 the first cache subsystem is a level-two (L2) cache subsystem; and   the second cache subsystem is a level-one (L1) cache subsystem.