US2023421998A1PendingUtilityA1

Video decoder with inline downscaler

Assignee: QUALCOMM INCPriority: Mar 31, 2021Filed: Sep 1, 2023Published: Dec 28, 2023
Est. expiryMar 31, 2041(~14.7 yrs left)· nominal 20-yr term from priority
H04W 4/029G01S 5/08G01S 5/0218H04W 24/10H04W 64/006H04B 17/318G01S 5/06G01S 5/0036G01S 5/0268G01S 5/0236
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Claims

Abstract

A device includes a memory configured to store video data. The device also includes a video decoder coupled to the memory and to a cache. The video decoder is configured to decode an input frame of the video data to generate a first video frame and includes an inline downscaler configured to generate a second video frame corresponding to the first video frame downscaled for display output.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A device comprising:
 a memory configured to store video data; and   a video decoder coupled to the memory and to a cache, the video decoder configured to decode an input frame of the video data to generate a first video frame and including an inline downscaler configured to generate a second video frame corresponding to the first video frame downscaled for display output.   
     
     
         2 . The device of  claim 1 , wherein the video decoder is configured to output the first video frame and the second video frame in parallel. 
     
     
         3 . The device of  claim 1 , wherein the video decoder is configured to select between storing the second video frame into the memory or into the cache. 
     
     
         4 . The device of  claim 1 , wherein the video decoder is configured to store a first portion of the second video frame into the memory and to store a second portion of the second video frame into the cache. 
     
     
         5 . The device of  claim 1 , wherein the first video frame is stored into the memory, and wherein the second video frame is stored into the cache. 
     
     
         6 . The device of  claim 1 , wherein the first video frame is stored into the memory based on a determination that the first video frame is a reference frame, and wherein storage of full-resolution non-reference frames to the memory is skipped. 
     
     
         7 . The device of  claim 1 , further comprising a display unit configured to receive the second video frame and to generate an output to a display device. 
     
     
         8 . The device of  claim 7 , wherein the display unit is configured to receive the second video frame from the cache. 
     
     
         9 . The device of  claim 7 , wherein the display unit is configured to receive the second video frame from the memory. 
     
     
         10 . The device of  claim 7 , wherein the display unit is configured to selectively receive the second video frame from the memory or from the cache. 
     
     
         11 . The device of  claim 7 , wherein the display unit is configured to receive a first portion of the second video frame from the memory and a second portion of the second video frame from the cache. 
     
     
         12 . The device of  claim 1 , further comprising a display device configured to display an output based on the second video frame. 
     
     
         13 . The device of  claim 1 , further comprising one or more processors that include the video decoder. 
     
     
         14 . The device of  claim 13 , further comprising a modem coupled to the one or more processors and configured to receive the video data. 
     
     
         15 . The device of  claim 13 , wherein the one or more processors are integrated in an extended reality headset device that is configured to display an output based on the second video frame. 
     
     
         16 . The device of  claim 13 , wherein the one or more processors are integrated in at least one of a mobile phone, a tablet computer device, or a wearable electronic device. 
     
     
         17 . The device of  claim 13 , wherein the one or more processors are integrated in a vehicle, the vehicle further including a display device configured to display an output based on the second video frame. 
     
     
         18 . The device of  claim 13 , wherein the one or more processors are included in an integrated circuit. 
     
     
         19 . A method of processing video data comprising:
 obtaining, at a video decoder, an input frame of video data;   decoding, at the video decoder, the input frame to generate a first video frame; and   generating, at an inline downscaler of the video decoder, a second video frame corresponding to the first video frame downscaled for display output.   
     
     
         20 . The method of  claim 19 , further comprising outputting the first video frame and the second video frame in parallel. 
     
     
         21 . The method of  claim 19 , further comprising selecting between storing the second video frame into a memory or into a cache. 
     
     
         22 . The method of  claim 19 , further comprising storing a first portion of the second video frame into a memory and storing a second portion of the second video frame into a cache. 
     
     
         23 . The method of  claim 19 , further comprising storing the first video frame into a memory and storing the second video frame into a cache. 
     
     
         24 . The method of  claim 19 , wherein the first video frame is stored into a memory based on a determination that the first video frame is a reference frame, and wherein storage of full-resolution non-reference frames to the memory is skipped. 
     
     
         25 . The method of  claim 19 , further comprising receiving the second video frame at a display unit and generating an output to a display device. 
     
     
         26 . The method of  claim 25 , wherein the second video frame is received from a cache. 
     
     
         27 . The method of  claim 25 , wherein the second video frame is received from a memory. 
     
     
         28 . The method of  claim 25 , wherein a first portion of the second video frame is received from a memory and a second portion of the second video frame is received from a cache. 
     
     
         29 . A non-transitory computer-readable medium comprising instructions that, when executed by one or more processors that include a video decoder, cause the one or more processors to:
 decode, at the video decoder, an input frame of video data to generate a first video frame; and   generate, at an inline downscaler of the video decoder, a second video frame corresponding to the first video frame downscaled for display output.   
     
     
         30 . An apparatus comprising:
 means for obtaining an input frame of video data; and   means for decoding the input frame to generate a first video frame, the means for decoding including means for inline downscaling to generate a second video frame corresponding to the first video frame downscaled for display output.

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