Power mosfet device having improved safe-operating area and on resistance, manufacturing process thereof and operating method thereof

Abstract

A power MOSFET device includes an active area accommodating a first body region and a second body region having a first and, respectively, a second conductivity value. The second value is higher than the first value. A first channel region is disposed in the first body region between a first source region and a drain region, and the first channel region has and having a first channel length. A second channel region is disposed in the second body region between a second source region and the drain region, and the second channel region has and having a second channel length smaller than the first channel length. A first device portion, having a first threshold voltage, includes the first channel region, and a second device portion, having a second threshold voltage higher than the first threshold voltage, includes the second channel region.

1 . A process for manufacturing a power MOSFET device, comprising:
 forming, in a semiconductor body having a first surface extending along a first direction and a second surface opposite the first surface, an active area;   forming, in the active area, extending into the semiconductor body from the first main surface, a first body region and a second body region, the first body region having a first conductivity type and a first conductivity value, and the second body region having the first conductivity type and a second conductivity value higher than the first conductivity value, wherein a portion of the semiconductor body underneath the first and the second body regions forms a drain region having a second conductivity type different from the first conductivity type;   forming, in the active area, extending into the semiconductor body from the first surface and within the first and the second body regions, a first source region and, respectively, a second source region having the second conductivity type, the first source region disposed adjacent to the first body region and the second source region disposed adjacent to the second body region; and   forming an insulated-gate region facing the first body region, the second body region, the first source region, the second source region and the drain region,   wherein the first body region arranged between the first source region and the drain region forms a first channel region adjacent to the insulated-gate region, and the second body region arranged between the second source region and the drain region forms a second channel region adjacent to the insulated-gate region, and   wherein the first channel region has a first channel length along the first direction, and the second channel region has a second channel length along the first direction that is smaller than the first channel length.   
     
     
         2 . The process according to  claim 1 , wherein the forming the first body region and the second body region comprises:
 forming the first body region by selectively introducing first dopant elements in the semiconductor body; and   forming the second body region by selectively introducing second dopant elements in the semiconductor body adjacently to and spaced from the first dopant elements.   
     
     
         3 . The manufacturing process according to  claim 2 , wherein the introducing first dopants comprises implanting a dose of first dopants within a range of 1·10 12  ions/cm 2  to 1·10 13  ions/cm 2 , and wherein the introducing second dopants comprises implanting a dose of second dopants within a range of 5·10 12  ions/cm 2  to 5·10 13  ions/cm 2 . 
     
     
         4 . The manufacturing process according to  claim 1 , comprising:
 forming an insulation region extending in the semiconductor body from the first surface and having a closed shape laterally surrounding the active area.   
     
     
         5 . The manufacturing process according to  claim 1 ,
 wherein the first body region and the second body region are separated from one another by the drain region,   wherein the drain region extends up to the first surface, the drain region including a surface portion at the first surface,   wherein the insulated-gate region extends over the semiconductor body and is vertically overlapping the surface portion of the drain region and partially overlapping the first and second source regions and the first and second body regions, and   wherein the first channel region and the second channel region face the first surface, the first source region spaced apart from the surface portion of the drain region by a first distance, equal to the first channel length, and the second source region spaced apart from the surface portion of the drain region by a second distance, equal to the second channel length.   
     
     
         6 . The method according to  claim 1 , wherein the insulated-gate region is a split-gate region. 
     
     
         7 . The method according to  claim 1 , comprising:
 forming a plurality of first device portions and a plurality of second device portions arranged, alternating with one another, in the form of an array or matrix.   
     
     
         8 . The method according to  claim 1 , comprising:
 forming a number of inactive insulated-gate regions in electrical contact with the first and the second source regions.   
     
     
         9 . The method according to  claim 8 , wherein the inactive insulated-gate regions are at least partially surrounded by respective interrupted oxide layers, and the inactive insulated-gate regions are in direct electrical contact with a source metallization region extending on the first surface and in direct electrical contact with the first and second source regions. 
     
     
         10 . A method for operating a power MOSFET device, the method comprising:
 biasing, in a first operating mode, an insulated-gate region at a first value of a gate voltage and at a value of a drain voltage correlated to a voltage applied between a drain region and source regions;   operating a first device portion in a saturation region;   generating a first value of a first current and a second device portion is in an inhibition state, the first value of the gate voltage being higher than a first threshold voltage and lower than a second threshold voltage; and   biasing, in a second operating mode, the insulated-gate region at a second value of the gate voltage and at the value of the drain voltage;   operating the first device portion in ohmic region;   generating a second value of the first current; and   operating the second device portion in ohmic region; and   generating a value of a second current, the second value of the gate voltage being higher than the second threshold voltage,   the first value of the first current is lower than a sum of the second value of the first current and of the value of the second current.   
     
     
         11 . The method of  claim 10  wherein the method includes the first device portion having the first threshold voltage includes a first body region, a first source region, a drain region, a first portion of the insulated-gate region, and a first channel region; and
 the second device portion includes a second body region, a second source region, the drain region, a second portion of the insulated-gate region, and a second channel region. 
 
     
     
         12 . The method of  claim 11  wherein the second device portion has the second threshold voltage that is higher than the first threshold voltage of the first device portion. 
     
     
         13 . A method, comprising:
 forming a power MOSFET device;   forming, a first body region and a second body region, the first body region having a first conductivity type, and the second body region having the first conductivity type;   forming a drain region having a second conductivity type different from the first conductivity type in a portion of a semiconductor body under the first and the second body regions;   forming in the first and the second body regions, a first source region and a second source region having the second conductivity type; and   forming an insulated-gate region facing the first body region, the second body region, the first source region, the second source region and the drain region;   forming a first channel region in the first body region between the first source region and the drain region;   forming a second channel region the second body region between the second source region and the drain region.   
     
     
         14 . The method of  claim 13  wherein the first body region having a first conductivity value, and the second body region having a second conductivity value higher than the first conductivity value. 
     
     
         15 . The method of  claim 14 , comprising:
 forming the first channel region adjacent to the insulated-gate region;   forming the second channel region adjacent to the insulated-gate region; and   forming the first channel region to have a first channel length along a first direction, and the second channel region to have a second channel length along the first direction that is smaller than the first channel length.   
     
     
         16 . The method of  claim 15 , comprising forming an insulation region extending in the semiconductor body from the first surface and having a closed shape laterally surrounding the active area. 
     
     
         17 . The method of  claim 16 , wherein the first body region and the second body region are separated from one another by the drain region, the drain region extends up to the first surface, the drain region including a surface portion at the first surface. 
     
     
         18 . The method of  claim 17  wherein the insulated-gate region extends over the semiconductor body and is vertically overlapping the surface portion of the drain region and partially overlapping the first and second source regions and the first and second body regions. 
     
     
         19 . The method of  claim 18  wherein the first channel region and the second channel region face the first surface, the first source region spaced apart from the surface portion of the drain region by a first distance, equal to the first channel length, and the second source region spaced apart from the surface portion of the drain region by a second distance, equal to the second channel length. 
     
     
         20 . The method of  claim 19 , comprising forming a number of inactive insulated-gate regions in electrical contact with the first and the second source regions, the inactive insulated-gate regions are at least partially surrounded by respective interrupted oxide layers, and the inactive insulated-gate regions are in direct electrical contact with a source metallization region extending on the first surface and in direct electrical contact with the first and second source regions.