Wide bandgap transistors with gate-source field plates

Abstract

A transistor comprising an active region having a channel layer, with source and drain electrodes formed in contact with the active region and a gate formed between the source and drain electrodes and in contact with the active region. A spacer layer is on at least part of the surface of the plurality of active region between the gate and the drain electrode and between the gate and the source electrode. A field plate is on the spacer layer and extends on the spacer and over the active region toward the drain electrode. The field plate also extends on the spacer layer over the active region and toward the source electrode. At least one conductive path electrically connects the field plate to the source electrode or the gate.

1 . A transistor, comprising:
 an active region comprising a channel layer;   a source electrode and a drain electrode in electrical contact with the active region;   a gate between the source and drain electrodes and on the active region;   a field plate that overlaps the gate and is electrically connected to the source electrode or the gate; and   a spacer layer between the gate and the field plate and on the active region.   
     
     
         2 . The transistor of  claim 1 , wherein the field plate is electrically connected to the source electrode by a conductive path that extends beyond a vertical projection of the active region. 
     
     
         3 . The transistor of  claim 1 , wherein the field plate is electrically connected to the gate by a conductive path that extends beyond a vertical projection of the active region. 
     
     
         4 . The transistor of  claim 1 , wherein the field plate is electrically connected to the source electrode by at least one conductive bus on the spacer layer. 
     
     
         5 . The transistor of  claim 1 , wherein the field plate is electrically connected to the gate by at least one conductive via in the spacer layer. 
     
     
         6 . The transistor of  claim 1 , wherein the field plate extends on a first portion of the spacer layer between the gate and the drain electrode a first distance L fd ,
 wherein the field plate extends on a second portion of the spacer layer between the gate and the source electrode a second distance L fs , and   wherein the first distance L fd  is greater than the second distance L fs .   
     
     
         7 . The transistor of  claim 1 , wherein the spacer layer extends on opposing side surfaces and an upper surface of the gate. 
     
     
         8 . The transistor of  claim 1 , wherein at least a portion of the gate is in the active region. 
     
     
         9 . The transistor of  claim 8 , further comprising a buffer layer and a barrier layer on a substrate,
 wherein the channel layer is at a heterointerface between the buffer layer and the barrier layer, and   wherein at least the portion of the gate is in the barrier layer.   
     
     
         10 . The transistor of  claim 1 , wherein the field plate is a source field plate,
 wherein the transistor further comprises a drain field plate spaced apart from the source field plate,   wherein the source field plate overlaps a first side surface of the gate that faces the source electrode, and   wherein the drain field plate overlaps a second side surface of the gate that faces the drain electrode.   
     
     
         11 . The transistor of  claim 1 , further comprising a buffer layer and a barrier layer on a substrate,
 wherein the channel layer is at a heterointerface between the buffer layer and the barrier layer, and   wherein the spacer layer is on an entirety of an upper surface of the barrier layer.   
     
     
         12 . The transistor of  claim 1 , wherein the spacer layer comprises at least one dielectric layer. 
     
     
         13 . The transistor of  claim 1 , wherein the channel layer is on a silicon carbide substrate, and
 wherein at least a portion of the gate is in the channel layer.   
     
     
         14 . A transistor, comprising:
 an active region comprising a channel layer, the channel layer comprising a two dimensional electron gas (2DEG) region;   a source electrode and a drain electrode in electrical contact with the active region;   a gate between the source and drain electrodes and on the active region;   a field plate that overlaps the gate and is electrically connected to the source electrode or the gate; and   a spacer layer that extends between the source and drain electrodes on the active region.   
     
     
         15 . The transistor of  claim 14 , wherein the spacer layer extends between the gate and the field plate, and
 wherein the field plate comprises a conductive material.   
     
     
         16 . The transistor of  claim 14 , wherein the field plate is electrically connected to the source electrode or the gate by a conductive path that extends beyond a vertical projection of the active region. 
     
     
         17 . A transistor, comprising:
 an active region comprising a channel layer, the channel layer comprising a two dimensional electron gas (2DEG) region;   a source electrode and a drain electrode in electrical contact with the active region;   a gate between the source and drain electrodes and on the active region;   a first field plate that overlaps the gate and is electrically connected to the source electrode or the gate;   a first spacer layer on the active region between the gate and the drain electrode and between the gate and the source electrode;   a second spacer layer on the first field plate; and   a second field plate on the second spacer layer.   
     
     
         18 . The transistor of  claim 17 , wherein the second field plate is electrically connected to the source electrode or the gate, and
 wherein the first spacer layer extends between the gate and the first field plate.   
     
     
         19 . The transistor of  claim 17 , wherein the second field plate extends from a vertical edge of the gate toward the drain electrode by a distance L fd2  that is in a range from 0.2 to 5 microns. 
     
     
         20 . The transistor of  claim 17 , wherein the second field plate overlaps the first field plate and the gate, and
 wherein the second spacer layer is on an entirety of an upper surface of the first field plate and an upper surface of the first spacer layer.