Semiconductor structure and method for forming the same

Abstract

A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures vertically stacked and separated from one another, a source/drain feature adjacent to the plurality of nanostructures, and an inner spacer layer. The inner spacer layer includes a vertical portion interposing between the plurality of nanostructures and the source/drain feature and a plurality of horizontal portions interposing between the nanostructures. A source/drain junction is located in the vertical portion of the inner spacer layer and is spaced apart from the plurality of nanostructures by a distance.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a plurality of nanostructures vertically stacked and separated from one another;   a source/drain feature adjacent to the plurality of nanostructures; and   an inner spacer layer including a vertical portion interposing between the plurality of nanostructures and the source/drain feature and a plurality of horizontal portions interposing between the nanostructures, wherein a source/drain junction is located in the vertical portion of the inner spacer layer and is spaced apart from the plurality of nanostructures by a distance.   
     
     
         2 . The semiconductor structure as claimed in  claim 1 , wherein the inner spacer layer is made of a semiconductor material. 
     
     
         3 . The semiconductor structure as claimed in  claim 1 , further comprising:
 an interfacial layer including a first portion along a bottom surface of a first nanostructure in the plurality of nanostructures, a second portion along a top surface of a second nanostructure in the plurality of nanostructures, and a third portion connecting the first portion of the interfacial layer to the second portion of the interfacial layer.   
     
     
         4 . The semiconductor structure as claimed in  claim 3 , wherein the third portion of the interfacial layer is in direct contact with one of the horizontal portions of the inner spacer layer. 
     
     
         5 . The semiconductor structure as claimed in  claim 1 , further comprising:
 a gate spacer layer above the plurality of nanostructures, wherein the gate spacer layer is direct contact with the horizontal portions of the inner spacer layer.   
     
     
         6 . The semiconductor structure as claimed in  claim 1 , wherein the inner spacer layer is doped. 
     
     
         7 . The semiconductor structure as claimed in  claim 6 , wherein a dopant concentration of the inner spacer layer is in a range from about 1×10 19  cm −3  to about 9×10 19  cm −3 . 
     
     
         8 . The semiconductor structure as claimed in  claim 1 , wherein the inner spacer layer further includes a bottom portion below the source/drain feature. 
     
     
         9 . A semiconductor structure, comprising:
 a gate stack wrapping around a plurality of nanostructures;   a gate spacer layer alongside the gate stack;   a semiconductor inner spacer layer alongside plurality of nanostructures below the gate spacer layer; and   a source/drain feature alongside the semiconductor inner spacer layer, wherein a source/drain junction vertically extends in the semiconductor inner spacer and between extension lines of sidewalls of the gate spacer layer.   
     
     
         10 . The semiconductor structure as claimed in  claim 9 , wherein the source/drain junction extends through a topmost one of the nanostructures. 
     
     
         11 . The semiconductor structure as claimed in  claim 9 , wherein the gate stack includes an interfacial layer, a high-k gate dielectric layer over the interfacial layer and a gate electrode layer over the high-k gate dielectric layer. 
     
     
         12 . The semiconductor structure as claimed in  claim 11 , wherein the interfacial layer is spaced apart from the semiconductor inner spacer layer by a distance. 
     
     
         13 . The semiconductor structure as claimed in  claim 11 , wherein in a cross-sectional view, the interfacial layer has a closed-loop profile, and the high-k gate dielectric layer is located within the closed-loop profile of the interfacial layer. 
     
     
         14 . The semiconductor structure as claimed in  claim 9 , further comprising:
 a fin element below the plurality of nanostructures; and   an isolation structure surrounding the fin element.   
     
     
         15 . A method for forming a semiconductor structure, comprising:
 forming a fin structure in which first semiconductor layers and second semiconductor layers are stacked alternatingly;   etching the fin structure to form a recess;   recessing the first semiconductor layers to form notches between the second semiconductor layers;   forming an inner spacer layer to cover sidewalls of the second semiconductor layers and fill the notches;   forming a source/drain feature in the source/drain recess; and   driving a dopant from the source/drain feature into the inner spacer layer to form a source/drain junction, wherein the source/drain junction vertically extends through a portion of the inner spacer layer covering the sidewalls of the second semiconductor layers.   
     
     
         16 . The method for forming the semiconductor structure as claimed in  claim 15 , further comprising:
 removing the first semiconductor layers to expose the second semiconductor layers and the inner spacer layer; and   oxidizing the second semiconductor layers and the inner spacer layer to form an interfacial layer.   
     
     
         17 . The method for forming the semiconductor structure as claimed in  claim 16 , wherein the interfacial layer is formed on exposed surfaces of the second semiconductor layers and exposed surfaces of the inner spacer layer. 
     
     
         18 . The method for forming the semiconductor structure as claimed in  claim 15 , wherein the inner spacer layer is made of a semiconductor material. 
     
     
         19 . The method for forming the semiconductor structure as claimed in  claim 15 , wherein a dopant concentration of the inner spacer layer is less than about 10 14  cm −3 . 
     
     
         20 . The method for forming the semiconductor structure as claimed in  claim 15 , wherein the inner spacer layer is further formed on a bottom of the recess.