US2023413624A1PendingUtilityA1

Display device

Assignee: SAMSUNG DISPLAY CO LTDPriority: Dec 24, 2020Filed: Sep 6, 2023Published: Dec 21, 2023
Est. expiryDec 24, 2040(~14.4 yrs left)· nominal 20-yr term from priority
H10D 30/6734H10K 59/12H10K 59/65H10K 59/131H10D 86/60H10D 86/423H10D 86/471H10D 86/441H10D 30/6755H10D 30/6745H10D 30/6731H10D 86/451H10K 59/1213H01L 29/7869G09G 3/20G09G 3/3266G09G 3/32G09F 9/30G09F 9/33G09G 3/3208G09G 2300/0426
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Claims

Abstract

A display device includes: a substrate in which a transmission area, a display area, a non-display area and the display area, and a peripheral area are defined; pixels arranged on the display area; initialization gate lines and compensation gate lines extending along pixel rows; gate driving circuits disposed on the peripheral area; and gate connection lines disposed on the non-display area. A k-th gate driving circuit among the gate driving circuits simultaneously drives m-th and (m+1)-th initialization gate lines and n-th and (n+1)-th compensation gate lines. First portions of the n-th and (n+1)-th compensation gate lines and second portions of the n-th and (n+1)-th compensation gate lines, which are physically apart from each other by the transmission area, are electrically connected to each other through a first gate connection line among gate connection lines.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A display device comprising:
 a substrate in which a transmission area, a display area surrounding at least a portion of the transmission area, a non-display area between the transmission area and the display area, and a peripheral area outside the display area are defined;   a plurality of pixels arranged on the display area in pixel rows and pixel columns;   a plurality of initialization gate lines and a plurality of compensation gate lines respectively extending along the pixel rows;   a plurality of gate driving circuits disposed on the peripheral area and arranged in a direction of the pixel columns; and   a plurality of gate connection lines disposed on the non-display area,   wherein a k-th gate driving circuit among the plurality of gate driving circuits simultaneously drives m-th and (m+1)-th initialization gate lines among the plurality of initialization gate lines and n-th and (n+1)-th compensation gate lines among the plurality of compensation gate lines,   each of the m-th and (m+1)-th initialization gate lines and each of the n-th and (n+1)-th compensation gate lines include a first portion and a second portion which are physically apart from each other by the transmission area, and   the first portion and the second portion of each of the n-th and (n+1)-th compensation gate lines are electrically connected to each other through a first gate connection line among the plurality of gate connection lines,   wherein k and n are a natural number, and   m is a natural number greater than n+1.

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