External usb-c hardware failure protection

Abstract

USB ports such as Type-C USB-C ports in a personal computer (PC) or other computing device may be configured in dual-role port (DRP) mode. The DRP mode may provide the ability for a port to switch between providing power to an external device and receiving power from an external power source to the into the computing device. The voltage level received from an external power source is typically higher than the voltage level provided to an external device. When a USB device fails, it may apply the higher voltage level to an external device, which may cause the external device to fail. A voltage sense and device detection circuit which may be used to detect an internal failure and prevent a higher internal voltage to be applied to a USB device.

What is claimed is: 
     
         1 . A system comprising:
 a power delivery controller (PD) circuit configured to switchably couple a first voltage conductor to a voltage bus (VBUS) conductor on a universal serial bus (USB) port;   a transistor group configured to switchably couple a second voltage conductor to the VBUS conductor; and   a voltage sense circuit to:
 detect a short circuit between the first voltage conductor and the VBUS conductor; and 
 reduce a short circuit voltage between the first voltage conductor and the VBUS conductor in response to detecting the short circuit. 
   
     
     
         2 . The system of  claim 1 , further including a pull-down transistor configured to switchably couple the transistor group to a ground;
 wherein reducing the short circuit voltage includes causing the pull-down transistor to couple the transistor group to the ground.   
     
     
         3 . The system of  claim 2 , further including a fuse coupled between the transistor group and the pull-down transistor;
 wherein coupling the transistor group to the ground causes an open circuit at the fuse.   
     
     
         4 . The system of  claim 3 , wherein:
 the fuse includes a slow-blow fuse; and   a current rating of the slow-blow fuse is selected to cause the open circuit in response to a current level induced when the transistor group is coupled to the ground for a predetermined duration.   
     
     
         5 . The system of  claim 2 , wherein the detection of the short circuit includes:
 determining no USB device is connected to the USB port; and   determining that a first voltage on the first voltage conductor is coupled to the VBUS conductor while no USB device is connected to the USB port.   
     
     
         6 . The system of  claim 5 , further including a configuration channel conductor on the USB port;
 wherein determining that no USB device is connected to the USB port is based on a configuration indication received from the configuration channel conductor at the voltage sense circuit.   
     
     
         7 . The system of  claim 2 , further including a system-on-a-chip (SOC) to receive an indication of the detection of the short circuit from the voltage sense circuit. 
     
     
         8 . A method comprising:
 detecting a short circuit at a transistor group conductively coupled between a first voltage conductor and a first voltage conductor to a voltage bus (VBUS) conductor on a universal serial bus (USB) port, the short circuit detected at a voltage sense circuit; and   reducing a short circuit voltage between the first voltage conductor and the VBUS conductor in response to detecting the short circuit.   
     
     
         9 . The method of  claim 8 , wherein reducing the short circuit voltage includes causing a pull-down transistor to couple the transistor group to a ground. 
     
     
         10 . The method of  claim 9 , wherein coupling the transistor group to the ground includes causing an open circuit at a fuse coupled between the transistor group and the pull-down transistor. 
     
     
         11 . The method of  claim 10 , wherein:
 the fuse includes a slow-blow fuse; and   a current rating of the slow-blow fuse is selected to cause the open circuit in response to a current level induced when the transistor group is coupled to the ground for a predetermined duration.   
     
     
         12 . The method of  claim 8 , wherein the detection of the short circuit includes:
 determining no USB device is connected to the USB port; and   determining that a first voltage on the first voltage conductor is coupled to the VBUS conductor while no USB device is connected to the USB port.   
     
     
         13 . The method of  claim 12 , wherein determining that no USB device is connected to the USB port is based on a configuration indication received from a configuration channel conductor at the voltage sense circuit. 
     
     
         14 . The method of  claim 9 , further including receiving an indication of the detection of the short circuit at a system-on-a-chip (SOC) from the voltage sense circuit. 
     
     
         15 . At least one non-transitory machine-readable storage medium, comprising a plurality of instructions that, responsive to being executed with processor circuitry of a computer-controlled device, cause the processor circuitry to:
 detect a short circuit at a transistor group conductively coupled between a first voltage conductor and a first voltage conductor to a voltage bus (VBUS) conductor on a universal serial bus (USB) port, the short circuit detected at a voltage sense circuit; and   reduce a short circuit voltage between the first voltage conductor and the VBUS conductor in response to detecting the short circuit.   
     
     
         16 . The at least one non-transitory machine-readable storage medium of  claim 15 , wherein reducing the short circuit voltage includes causing a pull-down transistor to couple the transistor group to a ground. 
     
     
         17 . The at least one non-transitory machine-readable storage medium of  claim 16 , wherein coupling the transistor group to the ground includes causing an open circuit at a fuse coupled between the transistor group and the pull-down transistor. 
     
     
         18 . The at least one non-transitory machine-readable storage medium of  claim 17 , wherein:
 the fuse includes a slow-blow fuse; and   a current rating of the slow-blow fuse is selected to cause the open circuit in response to a current level induced when the transistor group is coupled to the ground for a predetermined duration.   
     
     
         19 . The at least one non-transitory machine-readable storage medium of  claim 15 , wherein the detection of the short circuit includes:
 determining no USB device is connected to the USB port; and   determining that a first voltage on the first voltage conductor is coupled to the VBUS conductor while no USB device is connected to the USB port.   
     
     
         20 . The at least one non-transitory machine-readable storage medium of  claim 19 , wherein determining that no USB device is connected to the USB port is based on a configuration indication received from a configuration channel conductor at the voltage sense circuit. 
     
     
         21 . The at least one non-transitory machine-readable storage medium of  claim 16 , the instructions further causing the processor circuitry to receive an indication of the detection of the short circuit at a system-on-a-chip (SOC) from the voltage sense circuit.