Semiconductor device having nanosheets

Abstract

Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;   a first transistor over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack of N nanosheets; and   a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack of M nanosheets, wherein N is different from M.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising
 an isolation region separating the first transistor and the second transistor.   
     
     
         3 . The semiconductor device of  claim 2 , wherein the isolation region further comprises a dielectric structure extending into the substrate between the first and second transistors. 
     
     
         4 . The semiconductor device of  claim 1 , wherein both N and M are integers and each have a value of from 1 to 5. 
     
     
         5 . The semiconductor device of  claim 1 , wherein
 an upper surface of the first portion of the substrate defines a first plane; and   an upper surface of the second portion of the substrate defines a second plane, wherein a first vertical offset exists between the first plane and the second plane.   
     
     
         6 . The semiconductor device of  claim 5 , wherein
 the first vertical offset is within a range of 10-60 nm; and   N and M satisfy a relationship N<M.   
     
     
         7 . The semiconductor device of  claim 5 , wherein
 the first vertical offset distance is at most twice a thickness of a single nanosheet.   
     
     
         8 . The semiconductor device of  claim 5 , further comprising:
 a third transistor over a third portion of the substrate, wherein the third transistor comprises a third nanosheet stack of O nanosheets, wherein O is different from each of N and M.   
     
     
         9 . The semiconductor device of  claim 8 , wherein
 an upper surface of the third portion of the substrate defines a third plane, wherein a second vertical offset distance exists between the second plane and the third plane.   
     
     
         10 . A semiconductor device comprising:
 a first transistor over a substrate, wherein the first transistor comprises a first plurality of nanosheets, the first transistor has a first sheet width, and the first transistor has a first power efficiency;   a second transistor over the substrate, wherein the second transistor comprises a second plurality of nanosheets, the second transistor has the first sheet width, and the second transistor has a second power efficiency different from the first power efficiency; and   an isolation structure between the first transistor and the second transistor.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the first transistor has a first maximum frequency, the second transistor has a second maximum frequency, and the first maximum frequency is different from the second maximum frequency. 
     
     
         12 . The semiconductor device of  claim 10 , wherein a thickness of the substrate below the first transistor is different from a thickness of the substrate below the second transistor. 
     
     
         13 . The semiconductor device of  claim 10 , wherein a height of the first plurality of nanosheets is different from a height of the second plurality of nanosheets. 
     
     
         14 . The semiconductor device of  claim 10 , wherein each of the first plurality of nanosheets comprises silicon germanium and silicon. 
     
     
         15 . The semiconductor device of  claim 10 , wherein a top-most surface of the first transistor is offset from a top-most surface of the second transistor in a direction perpendicular to a top surface of the substrate by equal to or less than about 10 nanometers (nm). 
     
     
         16 . The semiconductor device of  claim 10 , wherein the first width ranges from about 15 nm to about 70 nm. 
     
     
         17 . A semiconductor device comprising:
 a first transistor over a substrate, wherein the first transistor comprises a first plurality of nanosheets, and the first plurality of nanosheets has a first height;   a second transistor over the substrate, wherein the second transistor comprises a second plurality of nanosheets, the second plurality of nanosheets has a second height, and the second height is different from the first height; and   an isolation structure between the first transistor and the second transistor.   
     
     
         18 . The semiconductor device of  claim 17 , wherein a top-most surface of the first transistor is offset from a top-most surface of the second transistor in a direction perpendicular to a top surface of the substrate by equal to or less than about 10 nanometers (nm). 
     
     
         19 . The semiconductor device of  claim 17 , wherein each of the first plurality of nanosheets has a first width, each of the second plurality of nanosheets has a second width, and the second width is different from the first width. 
     
     
         20 . The semiconductor device of  claim 17 , wherein a first sidewall of the first plurality of nanosheets is aligned with a first sidewall of the second plurality of nanosheets in a first direction parallel to a top surface of the substrate, and a second sidewall of the first plurality of nanosheets is offset from a second sidewall of the second plurality of nanosheets in a second direction parallel to the top surface of the substrate.