Three-dimensional memory devices and methods for forming the same

Abstract

In certain aspects, a three-dimensional (3D) memory device includes a stack structure, and a slit structure extending. The stack structure includes interleaved conductive layers and dielectric layers. Edges of the interleaved conductive layers and dielectric layers define a staircase structure. Each one of the conductive layers has a thickened portion in the staircase structure. The thickened portion extends along a first direction. The slit structure extends through the stack structure and along a second direction perpendicular to the first direction, such that the slit structure cuts off at least one, but not all, of the thickened portions of the conductive layers.

What is claimed is: 
     
         1 . A three-dimensional (3D) memory device, comprising:
 a stack structure comprising interleaved conductive layers and dielectric layers, wherein edges of the interleaved conductive layers and dielectric layers define a staircase structure, and each one of the conductive layers has a thickened portion in the staircase structure, the thickened portion extending along a first direction; and   a slit structure extending through the stack structure and along a second direction perpendicular to the first direction, such that the slit structure cuts off at least one, but not all, of the thickened potions of the conductive layers.   
     
     
         2 . The 3D memory device of  claim 1 , wherein
 at least the thickened portion of a first conductive layer of the conductive layers is continuous along the first direction and spaced apart from the slit structure in the second direction; and   at least the thickened portion of a second conductive layer of the conductive layers is discontinuous along the first direction and cut off by the slit structure from the second direction.   
     
     
         3 . The 3D memory device of  claim 2 , further comprising a channel structure extending through the stack structure, wherein the first conductive layer is closer to a source end of the channel structure than the second conductive layer. 
     
     
         4 . The 3D memory device of  claim 3 , wherein the first conductive layer comprises a gate-induced-drain-leakage (GIDL) line, and the second conductive layer comprises a select gate line electrically disconnected from the GIDL line. 
     
     
         5 . The 3D memory device of  claim 3 , further comprising a semiconductor layer in contact with the channel structure, wherein the first conductive layer is closer to the semiconductor layer than the second conductive layer. 
     
     
         6 . The 3D memory device of  claim 5 , wherein the semiconductor layer comprises N-type doped polysilicon. 
     
     
         7 . The 3D memory device of  claim 2 , wherein a dimension of the first conductive layer in the second direction is greater than a dimension of the second conductive layer in the second direction. 
     
     
         8 . The 3D memory device of  claim 2 , further comprising a cut structure extending through the first conductive layer. 
     
     
         9 . The 3D memory device of  claim 8 , wherein the cut structure stops at the thickened portion of the first conductive layer. 
     
     
         10 . The 3D memory device of  claim 1 , wherein the thickened portions of the conductive layers comprise a metal. 
     
     
         11 . A three-dimensional (3D) memory device, comprising:
 a semiconductor layer;   a stack structure comprising interleaved conductive layers and dielectric layers, wherein edges of the interleaved conductive layers and dielectric layers define a staircase structure, and each one of the conductive layers has a thickened portion in the staircase structure, the thickened portion extending along a first direction; and   a channel structure extending through the stack structure and in contact with the semiconductor layer,   wherein at least the thickened portion of a first conductive layer of the conductive layers is continuous along the first direction; and   at least the thickened portion of a second conductive layer of the conductive layers is discontinuous along the first direction, the first conductive layer being closer to the semiconductor layer than the second conductive layer.   
     
     
         12 . The 3D memory device of  claim 11 , further comprising a slit structure extending through the stack structure and along a second direction perpendicular to the first direction, such that the slit structure cuts off the thickened portion of the second conductive layer from the second direction and is spaced away from the thickened portion of the first conductive layer in the second direction. 
     
     
         13 . A method for forming a three-dimensional (3D) memory device, comprising:
 forming a stack structure comprising interleaved first material layers and second material layers;   forming a staircase structure of the stack structure;   forming third material layers each disposed on a respective one of the first material layers in the staircase structure and extending along a first direction; and   forming a slit opening extending through the stack structure and along a second direction perpendicular to the first direction, such that the slit opening cuts off at least one, but not all, of the third material layers.   
     
     
         14 . The method of  claim 13 , further comprising depositing a spacer into the slit opening to form a slit structure. 
     
     
         15 . The method of  claim 14 , wherein
 the first and third material layers comprise a same dielectric material; and   the method further comprises prior to depositing the spacer, replacing the first material layers and the third material layers with conductive layers through the slit opening.   
     
     
         16 . The method of  claim 13 , further comprising forming a semiconductor layer, such that the stack structure is formed on the semiconductor layer. 
     
     
         17 . The method of  claim 16 , further comprising doping the semiconductor layer with an N-type dopant. 
     
     
         18 . The method of  claim 13 , wherein forming the stack structure comprises forming a first layer of the first material layers and a second layer of the first material layers above the first layer, such that the third material layer on the first layer is spaced apart from the slit structure in the second direction, and the third material layer on the second layer is cut off by the slit opening from the second direction. 
     
     
         19 . The method of  claim 18 , further comprising prior to forming the third material layers, forming a cut structure extending through the first layer of the first material layers and the second layer of the first material layers. 
     
     
         20 . The method of  claim 19 , wherein the slit opening is aligned with the cut structure in the first direction, such that the slit opening removes part of the cut structure extending through the second layer of the first material layers.