Semiconductor device and corresponding method

Abstract

A semiconductor device comprises at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads is exposed at a rear surface of the package molding material to provide electrically conductive pads. The electrically conductive pads comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.

1 . A semiconductor device, comprising:
 a leadframe including a set of electrically conductive leads;   a semiconductor die electrically coupled to said set of electrically conductive leads; and   package molding material molded over the semiconductor die and the electrically conductive leads of the leadframe, wherein at least a portion of the electrically conductive leads is not covered by the package molding material;   electrically conductive pads at said portion of the electrically conductive leads which are not covered by the package molding material;   a plating layer on the electrically conductive pads that forms first enlarged end portions wherein said plating layer extends at least partially over a rear surface of the package molding material;   wherein the first enlarged end portions are configured for coupling to a printed circuit board.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the electrically conductive leads comprise body portions embedded in the package molding material and said plating layer forming the first enlarged end portions protrudes from the body portions at the rear surface of the package molding material. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the plating layer forming the first enlarged end portions extends over the rear surface of the package molding material sidewise of said body portions for a length of 10 μm to 100 μm. 
     
     
         4 . The semiconductor device of  claim 2 , wherein the plating layer forming the first enlarged end portions extend over the rear surface of the package molding material sidewise of said body portions for a length of 50 μm to 70 μm. 
     
     
         5 . The semiconductor device of  claim 1 , wherein said plating layer forming the first enlarged end portions comprises copper. 
     
     
         6 . The semiconductor device of  claim 1 , wherein said plating layer forming the first enlarged end portions comprises at least one metal selected from the group consisting of: nickel, palladium and gold. 
     
     
         7 . The semiconductor device of  claim 1 , wherein a thickness of the plating layer forming said first enlarged end portions is in a range of 10 μm to 100 μm. 
     
     
         8 . The semiconductor device of  claim 1 , wherein a thickness of the plating layer forming said first enlarged end portions is in a range of 50 μm to 70 μm. 
     
     
         9 . The semiconductor device of  claim 1 , further comprising a metallic layer plated over the plating layer forming said first enlarged end portions. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the metallic layer comprises tin. 
     
     
         11 . The semiconductor device of  claim 1 , wherein said leadframe further comprises a thermally conductor to which the semiconductor die is mounted, wherein at least a portion of the thermally conductor that is not covered by the package molding material provides a thermally conductive pad; and wherein said plating layer is also present on the thermally conductive pad to form a second enlarged end portion extending at least partially over the rear surface of the package molding material. 
     
     
         12 . The semiconductor device of  claim 1 , configured as a quad-flat no-lead package. 
     
     
         13 . The semiconductor device of  claim 1 , configured as a land grid array package. 
     
     
         14 . A semiconductor device, comprising:
 a semiconductor die mounted to a thermally conductive pad and electrically coupled to a set of electrically conductive leads;   package molding material molded over the semiconductor die, the thermally conductive pad and the electrically conductive leads, wherein at least a portion of the thermally conductive pad is exposed at a rear surface of the package molding material; and   a plating layer on the thermally conductive pad forming an enlarged portion extending at least partially over the rear surface of the package molding material, wherein the enlarged portion is configured for coupling to a printed circuit board.   
     
     
         15 . The semiconductor device of  claim 14 , wherein the thermally conductive pad comprises a body portion embedded in the package molding material and the plating layer forming said enlarged end portion protrudes from the rear surface of the package molding material. 
     
     
         16 . The semiconductor device of  claim 15 , wherein the plating layer forming said enlarged end portion extends over the rear surface of the package molding material sidewise of said body portions for a length of 10 μm to 100 μm. 
     
     
         17 . The semiconductor device of  claim 15 , wherein the plating layer forming said enlarged end portion extends over the rear surface of the package molding material sidewise of said body portions for a length of 50 μm to 70 μm. 
     
     
         18 . The semiconductor device of  claim 15 , wherein the plating layer forming said enlarged end portion comprises at least one metal selected from the group consisting of: copper, nickel, palladium and gold. 
     
     
         19 . The semiconductor device of  claim 14 , wherein a thickness of plating layer forming said enlarged end portion is in a range of 10 μm to 100 μm. 
     
     
         20 . The semiconductor device of  claim 14 , wherein a thickness of the plating layer forming said enlarged end portion is in a range of 50 μm to 70 μm. 
     
     
         21 . The semiconductor device of  claim 14 , further comprising a metallic layer plated over the plating layer forming said enlarged end portion. 
     
     
         22 . The semiconductor device of  claim 21 , wherein the metallic layer comprises tin.