Method of manufacturing integrated circuit device

Abstract

A method includes forming a circuit region over a substrate. The circuit region includes at least one active region extending along a first direction, and at least one gate region extending across the at least one active region and along a second direction transverse to the first direction. At least one first input/output (TO) pattern and at least one second TO pattern are correspondingly formed in different first and second metal layers to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first TO pattern extends along a third direction oblique to both the first direction and the second direction. The at least one second TO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction.

What is claimed is: 
     
         1 . A method, comprising:
 forming a circuit region over a substrate, the circuit region comprising:
 at least one active region extending along a first direction; and 
 at least one gate region extending across the at least one active region and along a second direction transverse to the first direction; 
   forming, in a first metal layer, at least one first input/output (TO) pattern to electrically couple the circuit region to external circuitry outside the circuit region; and   forming, in a second metal layer different from the first metal layer, at least one second IO pattern to electrically couple the circuit region to external circuitry outside the circuit region,   wherein   the at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction, and   the at least one second IO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction.   
     
     
         2 . The method of  claim 1 , wherein
 the at least one first IO pattern comprises at least one of
 a signal IO pattern configured to communicate a data signal to or from the circuit region, or 
 a power IO pattern configured to supply a power supply voltage to the circuit region. 
   
     
     
         3 . The method of  claim 1 , wherein
 the circuit region has a boundary, and   the at least one first IO pattern is completely arranged within the boundary of the circuit region.   
     
     
         4 . The method of  claim 3 , further comprising:
 forming, in a third metal layer, an access pattern which extends along the first direction or the second direction, from outside the boundary of the circuit region to inside the boundary to overlap the at least one first IO pattern; and   forming a via electrically coupling the access pattern to the at least one first IO pattern.   
     
     
         5 . The method of  claim 3 , further comprising:
 forming, in the first metal layer, an extension pattern contiguous to the at least one first IO pattern and extending from inside the boundary of the circuit region to outside the boundary;   forming, in the second metal layer, a further pattern which extends along the fourth direction to overlap the extension pattern; and   forming a via electrically coupling the further pattern to the extension pattern.   
     
     
         6 . The method of  claim 5 , further comprising:
 forming a further circuit region over the substrate,   wherein the further pattern is an IO pattern of a further circuit region.   
     
     
         7 . The method of  claim 1 , wherein the at least one first IO pattern comprises a plurality of first IO patterns in the first metal layer, the method further comprising:
 forming, in a third metal layer, an access pattern which extends along the first direction or the second direction, across an entire width or height of the circuit region to overlap the plurality of first IO patterns; and   forming a plurality of vias electrically coupling the access pattern correspondingly to the plurality of first IO patterns.   
     
     
         8 . The method of  claim 3 , wherein the at least one first IO pattern comprises a plurality of first IO patterns in the first metal layer, the method further comprising:
 forming, in the second metal layer, a further pattern which extends along the fourth direction;   forming an extension pattern in the first metal layer, the extension pattern contiguous to one first IO pattern among the plurality of first IO patterns and extending from inside the boundary of the circuit region to outside the boundary to overlap the further pattern;   forming a first via electrically coupling the further pattern to the extension pattern;   forming, in a third metal layer, an access pattern which extends along the first direction or the second direction from outside the boundary of the circuit region to inside the boundary to overlap a further first IO pattern among the plurality of first IO patterns; and   forming a second via electrically coupling the access pattern to the further first IO pattern.   
     
     
         9 . The method of  claim 1 , wherein
 the fourth direction is oblique to the third direction.   
     
     
         10 . A method, comprising:
 forming a first core region over a substrate, the first core region comprising:
 at least one active region elongated along a first direction; and 
 at least one gate region extending across the at least one active region and elongated along a second direction transverse to the first direction; 
   forming a first ring region over the substrate, and surrounding the first core region; and   forming at least one first input/output (TO) pattern in the first ring region to electrically couple the first core region to external circuitry outside the first core region,   wherein the at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.   
     
     
         11 . The method of  claim 10 , further comprising:
 forming at least one second IO pattern in the first ring region to electrically couple the first core region to external circuitry outside the first core region,   wherein   the at least one second IO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction,   the at least one first IO pattern is formed in a first metal layer, and   the at least one second TO pattern is formed in a second metal layer different from the first metal layer.   
     
     
         12 . The method of  claim 11 , wherein
 the at least one first TO pattern overlaps the at least one second TO pattern.   
     
     
         13 . The method of  claim 10 , further comprising:
 forming a second core region over the substrate;   forming a second ring region over the substrate, and surrounding the second core region; and   forming at least one second TO pattern in the second ring region to electrically couple the second core region to external circuitry outside the second core region,   wherein   the at least one second TO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction,   the at least one first TO pattern is formed in a first metal layer,   the at least one second TO pattern is formed in a second metal layer different from the first metal layer,   the at least one first TO pattern overlaps the at least one second TO pattern, and   the method further comprises forming at least one via electrically coupling the at least one first TO pattern to the at least one second TO pattern.   
     
     
         14 . The method of  claim 13 , wherein
 the first ring region partially overlaps the second ring region, and   the first core region is adjacent the second core region in the first direction or the second direction.   
     
     
         15 . The method of  claim 10 , further comprising:
 forming a second core region over the substrate;   forming a second ring region over the substrate, and surrounding the second core region; and   forming at least one second IO pattern in the second ring region to electrically couple the second core region to external circuitry outside the second core region,   wherein   the at least one second IO pattern extends along the third direction and is formed in a same metal layer as the at least one first IO pattern, and   the method further comprises forming, in the metal layer, at least one extension pattern extending along the third direction and contiguous to both the at least one first IO pattern and the at least one second IO pattern to electrically couple the first core region to the second core region.   
     
     
         16 . The method of  claim 10 , further comprising:
 forming a second core region over the substrate;   forming a second ring region over the substrate, and surrounding the second core region; and   forming at least one second IO pattern in the second ring region to electrically couple the second core region to external circuitry outside the second core region,   wherein   the at least one second IO pattern extends along the third direction and is formed in a same first metal layer as the at least one first IO pattern,   the method further comprises forming, in a second metal layer different from the first metal layer, at least one access pattern,   the at least one access pattern extends along a fourth direction to overlap both the at least one first IO pattern and the at least one second IO pattern,   the fourth direction is oblique to both the first direction and the second direction, and is transverse to the third direction, and   the method further comprises
 forming a first via electrically coupling the access pattern to the at least one first IO pattern, and 
 forming a second via electrically coupling the access pattern to the at least one second IO pattern. 
   
     
     
         17 . The method of  claim 10 , further comprising:
 forming a second core region over a further substrate;   forming a second ring region over the further substrate, and surrounding the second core region;   forming at least one second IO pattern in the second ring region to electrically couple the second core region to external circuitry outside the second core region; and   stacking the substrate and the further substrate one on top another so that the first core region and the second core region are stacked one on top another, and the at least one first IO pattern overlaps the at least one second IO pattern,   wherein   the at least one second IO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction,   the at least one first IO pattern is formed in a first metal layer,   the at least one second IO pattern is formed in a second metal layer different from the first metal layer, and   the method further comprises forming at least one via electrically coupling the at least one first IO pattern to the at least one second IO pattern.   
     
     
         18 . A method, comprising:
 forming a circuit region over a substrate, the circuit region corresponding to an intellectual property (IP) block, the circuit region comprising:
 a boundary, 
 an elongated active region inside the boundary, and 
 a plurality of input/output (TO) patterns inside the boundary; 
   forming a first via over and electrically coupled to a first IO pattern among the plurality of IO patterns of the circuit region; and   forming, in a first metal layer over the first via, an access pattern which extends from outside the boundary of the circuit region to inside the boundary to overlap and electrically contact the first via,   wherein the access pattern and the first IO pattern form an acute angle therebetween.   
     
     
         19 . The method of  claim 18 , further comprising, before said forming the first via, forming, in a second metal layer over the substrate, a further pattern in the second metal layer and outside the boundary of the circuit region;
 forming a second via over and electrically coupled to the further pattern; and   forming, in a third metal layer over the second via,
 the plurality of IO patterns parallel to each other, and 
 an extension pattern which is contiguous to a second IO pattern among the plurality of IO patterns, and extends from inside the boundary of the circuit region to outside the boundary where the extension pattern overlaps and is electrically coupled to the second via, 
   wherein   the extension pattern extends transversely to and overlaps the further pattern in the second metal layer, and   the access pattern and the further pattern form an acute angle therebetween.   
     
     
         20 . The method of  claim 19 , wherein
 the further pattern is an IO pattern of a further circuit region corresponding to a further IP block.