Forward error correction code fec design method and related device

Abstract

This application provides example forward error correction (FEC) code design methods and example related devices. One example method includes determining a quantity of transmission lanes for transmitting data. A plurality of FEC working areas can be determined based on the quantity of transmission lanes, where a quantity of the plurality of FEC working areas is the same as the quantity of transmission lanes, and the plurality of FEC working areas are for performing check and error correction on the data. The data on a transmission lane of the transmission lanes can be evenly allocated to each of the plurality of FEC working areas. The data received by each of the plurality of FEC working areas can be processed by using the plurality of FEC working areas.

What is claimed is: 
     
         1 . A forward error correction (FEC) code design method, comprising:
 determining a quantity of transmission lanes for transmitting data;   determining a plurality of FEC working areas based on the quantity of transmission lanes, wherein a quantity of the plurality of FEC working areas is the same as the quantity of transmission lanes, and the plurality of FEC working areas are for performing check and error correction on the data;   evenly allocating data on a transmission lane of the transmission lanes to each of the plurality of FEC working areas; and   processing, by using the plurality of FEC working areas, data received by each of the plurality of FEC working areas.   
     
     
         2 . The method according to  claim 1 , wherein the evenly allocating data on a transmission lane of the transmission lanes to each of the plurality of FEC working areas comprises:
 dividing the data on the transmission lane to obtain a plurality of data blocks, wherein each data block comprises X characters, and X is a positive integer greater than 1; and   allocating the X characters comprised in each data block to the plurality of FEC working areas one by one.   
     
     
         3 . The method according to  claim 2 , wherein the processing, by using the plurality of FEC working areas, data received by each of the plurality of FEC working areas comprises:
 if the plurality of FEC working areas are in an encoding state, performing, by using each of the plurality of FEC working areas, calculation each time the X characters are received, to obtain Y FEC check bits corresponding to the X characters; or   if the plurality of FEC working areas are in a decoding state, performing, by using each of the plurality of FEC working areas, check and error correction on the X characters by using Y FEC check bits corresponding to the X characters.   
     
     
         4 . The method according to  claim 2 , wherein after the processing, by using the plurality of FEC working areas, data received by each of the plurality of FEC working areas, the method further comprises:
 inserting a data sequence between transport blocks transmitted on each of the transmission lanes, wherein a transport block comprises Z data blocks, the data sequence is for delimiting the data transmitted on the transmission lane, and Z is a positive integer greater than 1.   
     
     
         5 . The method according to  claim 1 , wherein a scramble reset (SR) sequence is comprised between transport blocks transmitted on each of the transmission lanes, a transport block comprises Z FEC blocks, and an FEC block comprises X characters and Y FEC check bits, wherein X, Y, and Z are positive integers greater than 1. 
     
     
         6 . A data processing apparatus, comprising:
 at least one processor; and   one or more memories coupled to the at least one processor and storing programming instructions for execution by the at least one processor to:
 determine a quantity of transmission lanes for transmitting data; 
 determine a plurality of forward error correction (FEC) working areas based on the quantity of transmission lanes, wherein a quantity of the plurality of FEC working areas is the same as the quantity of transmission lanes, and the plurality of FEC working areas are for performing check and error correction on the data; 
 evenly allocate data on a transmission lane of the transmission lanes to each of the plurality of FEC working areas; and 
 process, by using the plurality of FEC working areas, data received by each of the plurality of FEC working areas. 
   
     
     
         7 . The data processing apparatus according to  claim 6 , wherein evenly allocating the data on the transmission lane of the transmission lanes to each of the plurality of FEC working areas comprises:
 dividing the data on the transmission lane to obtain a plurality of data blocks, wherein each data block comprises X characters, and X is a positive integer greater than 1; and   evenly allocating the X characters comprised in each data block to the plurality of FEC working areas.   
     
     
         8 . The data processing apparatus according to  claim 7 , wherein processing, by using the plurality of FEC working areas, the data received by each of the plurality of FEC working areas comprises:
 if the plurality of FEC working areas are in an encoding state, perform, by using each of the plurality of FEC working areas, calculation each time the X characters are received, to obtain Y FEC check bits corresponding to the X characters; or   if the plurality of FEC working areas are in a decoding state, perform, by using each of the plurality of FEC working areas, check and error correction on the X characters by using Y FEC check bits corresponding to the X characters.   
     
     
         9 . The data processing apparatus according to  claim 7 , wherein the programming instructions are for execution by the at least one processor to:
 insert a data sequence between transport blocks transmitted on each of the transmission lanes, wherein a transport block comprises Z data blocks, the data sequence is for delimiting the data transmitted on the transmission lane, and Z is a positive integer greater than 1.   
     
     
         10 . The data processing apparatus according to  claim 6 , wherein a scramble reset (SR) sequence is comprised between transport blocks transmitted on each of the transmission lanes, a transport block comprises Z FEC blocks, and an FEC block comprises X characters and Y FEC check bits, wherein X, Y, and Z are positive integers greater than 1. 
     
     
         11 . A computer-readable storage medium storing programming instructions for execution by at least one processor, that when executed by the at least one processor, cause a computer to perform operations comprising:
 determining a quantity of transmission lanes for transmitting data;   determining a plurality of FEC working areas based on the quantity of transmission lanes, wherein a quantity of the plurality of FEC working areas is the same as the quantity of transmission lanes, and the plurality of FEC working areas are for performing check and error correction on the data;   evenly allocating data on a transmission lane of the transmission lanes to each of the plurality of FEC working areas; and   processing, by using the plurality of FEC working areas, data received by each of the plurality of FEC working areas.   
     
     
         12 . The computer-readable storage medium according to  claim 11 , wherein the evenly allocating data on a transmission lane of the transmission lanes to each of the plurality of FEC working areas comprises:
 dividing the data on the transmission lane to obtain a plurality of data blocks, wherein each data block comprises X characters, and X is a positive integer greater than 1; and   allocating the X characters comprised in each data block to the plurality of FEC working areas one by one.   
     
     
         13 . The computer-readable storage medium according to  claim 12 , wherein the processing, by using the plurality of FEC working areas, data received by each of the plurality of FEC working areas comprises:
 if the plurality of FEC working areas are in an encoding state, performing, by using each of the plurality of FEC working areas, calculation each time the X characters are received, to obtain Y FEC check bits corresponding to the X characters; or   if the plurality of FEC working areas are in a decoding state, performing, by using each of the plurality of FEC working areas, check and error correction on the X characters by using Y FEC check bits corresponding to the X characters.   
     
     
         14 . The computer-readable storage medium according to  claim 12 , wherein after the processing, by using the plurality of FEC working areas, data received by each of the plurality of FEC working areas, the operations further comprise:
 inserting a data sequence between transport blocks transmitted on each of the transmission lanes, wherein a transport block comprises Z data blocks, the data sequence is for delimiting the data transmitted on the transmission lane, and Z is a positive integer greater than 1.   
     
     
         15 . The computer-readable storage medium according to  claim 11 , wherein a scramble reset (SR) sequence is comprised between transport blocks transmitted on each of the transmission lanes, a transport block comprises Z FEC blocks, and an FEC block comprises X characters and Y FEC check bits, wherein X, Y, and Z are positive integers greater than 1.