Capacitor structure and method for fabricating the same

Abstract

This invention provides a capacitor structure includes a U-shaped bottom electrode having a cap dielectric provided at its open end, a top electrode and a capacitor dielectric layer interposed between the bottom electrode and the top electrode to constitute an outer capacitor around a cylinder type solid inner capacitor, and the outer capacitor and the inner capacitor are divided by the cap dielectric. The cylinder type solid inner capacitor and the outer capacitor are fabricated separately so that the cylinder type solid inner capacitor may support its own weight to prevent its structure from being damaged during the fabrication of the capacitor.

What is claimed is: 
     
         1 . A capacitor structure, comprising:
 a U-shaped bottom electrode having two spaced vertical legs and a base connected with the two vertical legs, each of the vertical legs having a cap dielectric disposed on its one end away from the base;   a capacitor dielectric layer conformally formed on sidewall surfaces of the vertical legs of the bottom electrode and a surface of the base of the bottom electrode facing the cap dielectric as well as sidewall surfaces of the cap dielectric with uncovering a top of the cap dielectric away from the vertical leg; and   a top electrode covering the capacitor dielectric layer and the top of the cap dielectric so that the capacitor dielectric layer is interposed between the top electrode and the bottom electrode.   
     
     
         2 . The capacitor structure of  claim 1 , wherein the cap dielectric comprising silicon nitride (SiN). 
     
     
         3 . The capacitor structure of  claim 1 , wherein the bottom electrode comprises titanium nitride (TiN). 
     
     
         4 . The capacitor structure of  claim 1 , wherein the top electrode comprises polysilicon material. 
     
     
         5 . A capacitor structure for DRAM with crown capacitors, comprising:
 an array of capacitor cells, each of the capacitor cells is configured to a capacitor structure as claimed in  claim 1 .   
     
     
         6 . The capacitor structure for DRAM with crown capacitors of  claim 5 , wherein the capacitor cells share a common top electrode. 
     
     
         7 . The capacitor structure for DRAM with crown capacitors of  claim 5 , wherein each of the capacitor cells has its individual bottom electrode. 
     
     
         8 . A method for fabricating a capacitor structure with crown capacitors, comprising:
 providing a substrate having an array of conductive landing pads;   forming a first dielectric layer on the substrate;   forming a plurality of trenches in the first dielectric layer to expose the conductive landing pads, each of the trenches aligned over one of the conductive landing pads;   conformally forming a bottom electrode layer on the first dielectric layer;   conformally forming a first capacitor dielectric layer on the bottom electrode layer;   forming a first top electrode layer on the first capacitor dielectric layer so that the first capacitor dielectric layer is interposed between the first top electrode layer and the bottom electrode layer;   performing a first chemical mechanical polish process until the first dielectric layer, the bottom electrode layer, the first capacitor dielectric layer and the first top electrode layer are coplanar, whereby an array of inner capacitor predecessors are provided and each of the inner capacitor predecessors is aligned over one of the conductive landing pads, and each of the inner capacitor predecessors comprises the bottom electrode layer, the first top electrode layer and the first capacitor dielectric layer interposed between the bottom electrode layer and the first top electrode layer;   removing a portion of the bottom electrode layer to form an array of bottom electrodes and an array of recesses aligned over the bottom electrodes;   forming a cap dielectric layer to fill the recesses;   performing a second chemical mechanical polish process until the first dielectric layer, the cap dielectric layer, the first capacitor dielectric layer and the first top electrode layer are coplanar, whereby an array of inner capacitors are provided, each of the inner capacitors having the cap dielectric on one end of the bottom electrode opposing the conductive landing pad;   removing the first dielectric layer so that the inner capacitors are freestanding on the substrate;   conformally forming a second capacitor dielectric layer on the inner capacitors;   forming a second top electrode layer on the second capacitor dielectric layer so that the second capacitor dielectric layer is interposed between the second top electrode layer and the bottom electrode; and   performing a third chemical mechanical polish process until the first top electrode layer, the second top electrode layer, the cap dielectric, the first capacitor dielectric layer and the second capacitor dielectric layer are coplanar so as to form an array of outer capacitors, whereby an array of crown capacitors is provided, each of the crown capacitors comprises one of the outer capacitors around one of the inner capacitors.   
     
     
         9 . The method for fabricating a capacitor structure with crown capacitors of  claim 8 , wherein the step for forming the recesses aligned over the bottom electrodes is performed by an anisotropic etching process. 
     
     
         10 . The method for fabricating a capacitor structure with crown capacitors of  claim 8 , wherein the step for forming the first top electrode layer and the step for forming the second top electrode layer are performed by deposition with polysilicon material. 
     
     
         11 . The method for fabricating a capacitor structure with crown capacitors of  claim 10 , further comprising depositing a polysilicon layer on the array of the crown capacitors and forming a top electrode metal layer on the polysilicon layer. 
     
     
         12 . The method for fabricating a capacitor structure with crown capacitors of  claim 8 , wherein the step for forming the first dielectric layer is performed by deposition with silicon oxide. 
     
     
         13 . The method for fabricating a capacitor structure with crown capacitors of  claim 8 , wherein the step for forming the cap dielectric layer is performed by deposition with silicon nitride. 
     
     
         14 . The method for fabricating a capacitor structure with crown capacitors of  claim 8 , wherein the step for forming the first capacitor dielectric layer and the step for forming the second capacitor dielectric layer are performed with the same capacitor dielectric material. 
     
     
         15 . A method for fabricating a capacitor structure with crown capacitors, comprising:
 providing a substrate having an array of conductive landing pads;   forming a first dielectric layer on the substrate;   forming a plurality of trenches in the first dielectric layer to expose the conductive landing pads, each of the trenches aligned over one of the conductive landing pads;   conformally forming a bottom electrode layer on the first dielectric layer;   conformally forming a first capacitor dielectric layer on the bottom electrode layer;   forming a first top electrode layer on the first capacitor dielectric layer so that the first capacitor dielectric layer is interposed between the first top electrode layer and the bottom electrode layer;   performing a first chemical mechanical polish process until the first dielectric layer, the bottom electrode layer, the first capacitor dielectric layer and the first top electrode layer are coplanar, whereby an array of inner capacitor predecessors are provided and each of the inner capacitor predecessors is aligned over one of the conductive landing pads, and each of the inner capacitor predecessors comprises the bottom electrode layer, the first top electrode layer and the first capacitor dielectric layer interposed between the bottom electrode layer and the first top electrode layer;   removing the first dielectric layer so that the inner capacitor predecessors are freestanding on the substrate;   conformally forming a second capacitor dielectric layer on the inner capacitor predecessors;   forming a second top electrode layer on the second capacitor dielectric layer;   performing a second chemical mechanical polish process until the first top electrode layer, the second top electrode layer, the first capacitor dielectric layer, the second capacitor dielectric layer and the bottom electrode layer are coplanar;   removing a portion of the bottom electrode layer to form an array of bottom electrodes and an array of recesses aligned over the bottom electrodes;   forming a cap dielectric layer to fill the recesses; and   performing a third chemical mechanical process until the first top electrode layer, the second top electrode layer, the first capacitor dielectric layer, the second capacitor dielectric layer and the cap dielectric layer are coplanar so that an array of crown capacitors are provided, each of the crown capacitors comprises an outer capacitor around one of an inner capacitor, the outer capacitor has the second capacitor dielectric layer interposed between the second top electrode layer and the bottom electrode, the inner capacitor has the first capacitor dielectric layer interposed between the first top electrode layer and the bottom electrode, and the cap dielectric layer is provided at one end of the bottom electrode opposing the conductive landing pad.   
     
     
         16 . The method for fabricating a capacitor structure with crown capacitors of  claim 15 , wherein the step for forming the recesses aligned over the bottom electrodes is performed by an anisotropic etching process. 
     
     
         17 . The method for fabricating a capacitor structure with crown capacitors of  claim 15 , wherein the step for forming the first top electrode layer and the step for forming the second top electrode layer are performed by deposition with polysilicon material. 
     
     
         18 . The method for fabricating a capacitor structure with crown capacitors of  claim 17 , further comprising depositing a polysilicon layer on the array of the crown capacitors and forming a top electrode metal layer on the polysilicon layer. 
     
     
         19 . The method for fabricating a capacitor structure with crown capacitors of  claim 15 , wherein the step for forming the first dielectric layer is performed by deposition with silicon oxide. 
     
     
         20 . The method for fabricating a capacitor structure with crown capacitors of  claim 15 , wherein the step for forming the cap dielectric layer is performed by deposition with silicon nitride. 
     
     
         21 . The method for fabricating a capacitor structure with crown capacitors of  claim 15 , wherein the step for forming the first capacitor dielectric layer and the step for forming the second capacitor dielectric layer are performed with the same capacitor dielectric material.