Field Effect Transistor Constructions and Methods of Programming Field Effect Transistors to One Of At Least Three Different Programmed States

Abstract

A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

1 - 28 . (canceled) 
     
     
         29 . A method of programming a ferroelectric field effect transistor to one of at least three available different programmed states characterized by different V t  relative one another; the transistor comprising a semiconductive channel core, ferroelectric material proximate a periphery of the channel core, and a gate proximate a periphery of the ferroelectric material; the method comprising:
 applying a programming voltage to the gate that reverses polarization direction within the ferroelectric material at some circumferential location and not at another circumferential location to change V t  of the transistor from what it was prior to said applying.   
     
     
         30 . The method of  claim 29  wherein the ferroelectric material is directly against the channel core. 
     
     
         31 . The method of  claim 29  wherein the transistor comprises another dielectric directly against the periphery of the semiconductive channel core and another gate directly against a periphery of the another dielectric, the ferroelectric being dielectric being directly against a periphery of the another gate. 
     
     
         32 . The method of  claim 31  wherein the another dielectric is devoid of any ferroelectric material. 
     
     
         33 . A method of programming a ferroelectric field effect transistor to one of at least four available different programmed states characterized by different V t  relative one another; the transistor comprising a semiconductive channel core having at least four radially outermost surfaces that are straight along at least a majority of their respective circumferential lengths, ferroelectric material proximate the outermost surfaces, and a gate proximate a periphery of the ferroelectric material; the method comprising:
 applying a programming voltage to the gate that reverses polarization direction within the ferroelectric material that is over a first two of diametrically opposed of the at least four surfaces but not reversing polarization direction within the ferroelectric material that is over a second two of diametrically opposed of the at least four surfaces.   
     
     
         34 . A method of programming a field effect transistor to one of at least three available different programmed states characterized by different V t  relative one another; the transistor comprising a semiconductive channel core, tunnel dielectric proximate a periphery of the channel core, charge trapping material proximate a periphery of the tunnel dielectric, outer dielectric proximate a periphery of the charge trapping material, and conductive control gate material proximate a periphery of the outer dielectric; the method comprising:
 applying a programming voltage to the control gate that injects different quanta of electrons into the charge trapping material at different circumferential locations to change V t  of the transistor from what it was prior to said applying.   
     
     
         35 . A flash field effect transistor construction comprising:
 a semiconductive channel core;   a source/drain region at opposite ends of the channel core;   a control gate completely surrounding the channel core;   control gate insulative material completely surrounding the channel core radially inward of the control gate;   charge trapping material completely surrounding the channel core radially inward of the control gate insulative material; and   a tunnel insulator completely surrounding the channel core radially inward of the charge trapping material, the tunnel insulator having local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery.   
     
     
         36 . A field effect transistor construction, comprising:
 a semiconductive channel core;   a source/drain region at opposite ends of the channel core, the channel core comprising a minimum channel length there-through from an edge of one of the source/drain regions to an edge of the other source/drain region;   a gate construction proximate a periphery of the channel core, the gate construction comprising:   outer conductive material proximate the channel core periphery;   outer ferroelectric material proximate the channel core periphery radially inward of the outer conductive material, the outer ferroelectric material having local regions radially there-through of different radial thickness that individually extend along all of the minimum channel length at different circumferential locations relative to the channel core periphery;   inner conductive material proximate the channel core periphery radially inward of the outer ferroelectric material; and   inner dielectric radially between the inner conductive material and the channel core.   
     
     
         37 . The field effect transistor construction of  claim 36  wherein the inner dielectric comprises a first pair of opposite sides intersecting a second pair of opposite sides at corners, the first pair of opposite sides comprising a thickness different from a thickness of the second pair of opposite sides. 
     
     
         38 . The field effect transistor construction of  claim 36  wherein the inner conductive material is against the inner dielectric. 
     
     
         39 . The field effect transistor construction of  claim 36  wherein the inner conductive material is against the outer ferroelectric material. 
     
     
         40 . The field effect transistor construction of  claim 36  wherein the inner conductive material is against the inner dielectric and against the outer ferroelectric material. 
     
     
         41 . The field effect transistor construction of  claim 36  wherein the inner conductive material comprises the same composition as the outer conductive material. 
     
     
         42 . The field effect transistor construction of  claim 36  wherein the inner conductive material comprises a composition different from a composition of the outer conductive material.