Pin access hybrid cell height design and system

Abstract

A method of generating a layout diagram for an integrated circuit includes arranging a plurality of cells in the layout diagram, wherein each cell of the plurality of cells comprises a first power rail along a first boundary and a second power rail along a second boundary, and the first boundary is spaced from the second boundary in a first direction. The method further includes placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells in accordance with a design rule, wherein a first cell pin of the plurality of cell pins has a first end spaced from both the first power rail and the second power rail in the first direction.

What is claimed is: 
     
         1 . A method of generating a layout diagram for an integrated circuit, the method comprising:
 arranging a plurality of cells in the layout diagram, wherein each cell of the plurality of cells comprises a first power rail along a first boundary and a second power rail along a second boundary, and the first boundary is spaced from the second boundary in a first direction; and   placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells in accordance with a design rule, wherein a first cell pin of the plurality of cell pins has a first end spaced from both the first power rail and the second power rail in the first direction.   
     
     
         2 . The method of  claim 1 , wherein placing the plurality of cell pins comprises placing a second cell pin of the plurality of cell pins having a second end aligned with an edge of the first power rail outside the first cell. 
     
     
         3 . The method of  claim 1 , wherein placing the plurality of cell pins comprises placing the first cell pin extending beyond the first power rail in the first direction. 
     
     
         4 . The method of  claim 1 , wherein placing the plurality of cell pins comprises placing the plurality of cell pins on a metal layer farther from a substrate than the first power rail. 
     
     
         5 . The method of  claim 1 , further comprising retrieving the plurality of cells from a cell library. 
     
     
         6 . The method of  claim 1 , wherein placing the plurality of cell pins comprises placing the first cell pin extending only in the first direction. 
     
     
         7 . The method of  claim 1 , wherein placing the plurality of cell pins comprises placing the plurality of cell pins using an automatic placement routing (APR) tool. 
     
     
         8 . The method of  claim 1 , further comprising fabricating at least one mask based on the layout diagram for forming the integrated circuit. 
     
     
         9 . A method of generating a layout diagram for an integrated circuit, the method comprising:
 arranging a plurality of cells in the layout diagram, wherein each cell of the plurality of cells comprises a first power rail along a first boundary and a second power rail along a second boundary, and the first boundary is spaced from the second boundary in a first direction; and   placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells in accordance with a design rule, wherein a first cell pin of the plurality of cell pins overlaps the first power rail between the adjacent cells of the plurality of cells.   
     
     
         10 . The method of  claim 9 , further comprising placing a via at a first via placement point of the plurality of selected via placement points, wherein the via overlaps the first cell pin. 
     
     
         11 . The method of  claim 9 , wherein placing the plurality of cell pins comprises placing a second cell pin of the plurality of cell pins entirely within a first cell of the plurality of cells. 
     
     
         12 . The method of  claim 11 , wherein placing the second cell pin comprises placing the second cell pin overlapping with a first via placement point of the plurality of selected via placement points. 
     
     
         13 . The method of  claim 9 , wherein arranging the plurality of cells comprises abutting the adjacent cells in the first direction. 
     
     
         14 . The method of  claim 9 , wherein placing the plurality of cell pins comprises placing the plurality of cell pins satisfying a minimum end-to-end spacing requirement. 
     
     
         15 . The method of  claim 9 , further comprising identifying a location of each of a plurality of via placement points, comprising the plurality of selected via placement points, based on an intersection of conductive lines at different levels of the integrated circuit. 
     
     
         16 . The method of  claim 15 , further comprising selecting each of the plurality of selected via placement points from the plurality of via placement points based on a spacing requirement. 
     
     
         17 . The method of  claim 9 , further comprising instructing at least one manufacturing tool to manufacture the integrated circuit including the first pin cell. 
     
     
         18 . A system for generating an integrated circuit, the system comprising:
 a non-transitory computer readable medium configured to store instructions thereon; and   a processor connected to the non-transitory computer readable medium, wherein the processor is configured to execute the instructions for:
 arranging a plurality of cells in the layout diagram, wherein each cell of the plurality of cells comprises a first power rail along a first boundary and a second power rail along a second boundary, and the first boundary is spaced from the second boundary in a first direction; and 
 placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells in accordance with a design rule, wherein a first cell pin of the plurality of cell pins has a first end spaced from both the first power rail and the second power rail in the first direction. 
   
     
     
         19 . The system of  claim 18 , wherein the processor is further configured to execute the instructions for arranging the plurality of cells by abutting the adjacent cells in the first direction. 
     
     
         20 . The system of  claim 18 , wherein the processor is further configured to execute the instructions for instructing at least one manufacturing tool to manufacture the integrated circuit including the first pin cell.