US2023396361A1PendingUtilityA1

Error check-based synchronization and broadcast channel

Assignee: INTERDIGITAL PATENT HOLDINGS INCPriority: Jan 6, 2017Filed: Aug 22, 2023Published: Dec 7, 2023
Est. expiryJan 6, 2037(~10.4 yrs left)· nominal 20-yr term from priority
H04W 56/0015H04W 48/16H04L 5/0051H04J 11/0076H03M 13/2957H03M 13/13H03M 13/1102H03M 13/09H04L 1/0061H04J 11/0073H04L 1/0072H04L 69/324H04L 5/0053H04L 1/0041H04L 1/0057H04L 5/005H04L 5/0094
77
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Systems, methods, and instrumentalities are disclosed for error check-based synchronization. Physical Broadcast Channel (PBCH) data may be determined. A scrambling (e.g., a first scrambling) of the PBCH data may be scrambled via a sequence (e.g., a first sequence). The first sequence may be based on a cell ID and/or timing information. Error check bits may be attached to the scrambled PBCH data and to the timing information. The error check bits may include one or more cyclic redundancy check (CRC) bits. The scrambled PBCH data, the timing information (e.g., the unscrambled timing information), and/or the attached error check bits may be polar encoded. The polar encoding may result in polar encoded bits. A scrambling (e.g., a second scrambling) of the polar encoded bits may be scrambled via a sequence (e.g., a second sequence). The first sequence and the second sequence may be different. The polar encoded bits may be transmitted.

Claims

exact text as granted — not AI-modified
1 . (canceled) 
     
     
         2 . A wireless transmit/receive unit (WTRU), the WTRU comprising:
 a processor configured to:   receive a transmission;   descramble the transmission using a first sequence associated with at least a synchronization signal (SS) block index corresponding to the transmission;   decode the transmission to generate timing information, wherein the transmission is polar encoded; and   generate a PBCH payload, wherein the PBCH payload is generated based on at least the timing information.   
     
     
         3 . The WTRU of  claim 2 , wherein the transmission comprises cyclic redundancy check (CRC) bits. 
     
     
         4 . The WTRU of  claim 3 , wherein the processor is configured to perform an error check of the timing information using the cyclic redundancy check bits. 
     
     
         5 . The WTRU of  claim 2 , wherein the first bits are descrambled based on cell information. 
     
     
         6 . The WTRU of  claim 5 , wherein the cell information is a cell identity. 
     
     
         7 . The WTRU of  claim 2 , wherein the timing information comprises frame boundary information and SS block index information. 
     
     
         8 . The WTRU of  claim 2 , wherein the timing information comprises a system frame number. 
     
     
         9 . A method comprising:
 receiving a transmission;   descrambling the transmission using a first sequence associated with at least a synchronization signal (SS) block index corresponding to the transmission;   decoding the transmission to generate timing information, wherein the transmission is polar encoded; and   generating a PBCH payload, wherein the PBCH payload is generated based on at least the timing information.   
     
     
         10 . The method of  claim 9 , wherein the transmission comprises cyclic redundancy check (CRC) bits. 
     
     
         11 . The method of  claim 10 , wherein the processor is configured to perform an error check of the timing information using the cyclic redundancy check bits. 
     
     
         12 . The method of  claim 9 , wherein the first bits are descrambled based on cell information. 
     
     
         13 . The method of  claim 12 , wherein the cell information is a cell identity. 
     
     
         14 . The method of  claim 9 , wherein the timing information comprises frame boundary information and SS block index information. 
     
     
         15 . The method of  claim 9 , wherein the timing information comprises a system frame number. 
     
     
         16 . A network device, comprising:
 a processor configured to:   determine information that comprises a combination of a data and a first sequence;   associate error check bits with the information that comprises the combined data and first sequence;   polar encode the information that comprises the combined data and first sequence and the associated error check bits, wherein the polar encoding results in polar encoded bits;   perform a scrambling on the polar encoded bits via a second sequence, wherein the second sequence is a function of a cell information and an SS block index; and   transmit the scrambled polar encoded bits.   
     
     
         17 . The network device of  claim 16 , wherein the information further comprises synchronization information. 
     
     
         18 . The network device of  claim 16 , wherein the first sequence and the second sequence are different. 
     
     
         19 . The network device of  claim 16 , wherein the data is physical broadcast channel data. 
     
     
         20 . The network device of  claim 19 , wherein the physical broadcast channel data is new radio (NR)-PBCH data.

Join the waitlist — get patent alerts

Track US2023396361A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.