Trenchless single-photon avalanche diodes

Abstract

Structures for a single-photon avalanche diode and methods of forming a structure for a single-photon avalanche diode. The structure includes a semiconductor substrate having a top surface, a semiconductor layer on the top surface of the semiconductor substrate, a light-absorbing layer on a portion of the semiconductor layer, and a doped region in the portion of the semiconductor layer. The doped region is positioned in the portion of the semiconductor layer adjacent to the light-absorbing layer.

What is claimed is: 
     
         1 . A structure comprising:
 a semiconductor substrate having a top surface;   a semiconductor layer on the top surface of the semiconductor substrate;   a first doped region in the semiconductor substrate adjacent to the semiconductor layer; and   a deep trench isolation structure coupled to the first doped region, the deep trench isolation structure surrounding a portion of the semiconductor layer, and the deep trench isolation structure including a dielectric liner and a conductor layer surrounded by the dielectric liner.   
     
     
         2 . The structure of  claim 1  wherein the dielectric liner is positioned in a lateral direction between the conductor layer and the semiconductor layer. 
     
     
         3 . The structure of  claim 1  wherein the deep trench isolation structure is positioned fully over the top surface of the semiconductor substrate. 
     
     
         4 . The structure of  claim 1  wherein the semiconductor layer has a thickness, and the deep trench isolation structure has a height that is substantially equal to the thickness of the portion of the semiconductor layer. 
     
     
         5 . The structure of  claim 1  wherein the semiconductor layer has a thickness, and the deep trench isolation structure has a height that is equal to the thickness of the portion of the semiconductor layer. 
     
     
         6 . The structure of  claim 1  further comprising:
 a light-absorbing layer on the portion of the semiconductor layer. 
 
     
     
         7 . The structure of  claim 6  wherein the light-absorbing layer comprises germanium. 
     
     
         8 . The structure of  claim 6  wherein the light-absorbing layer comprises a first material, and further comprising:
 a cap layer on the light-absorbing layer, the cap layer comprising a second material different from the first material. 
 
     
     
         9 . The structure of  claim 6  wherein the deep trench isolation structure is laterally spaced from the light-absorbing layer by a gap. 
     
     
         10 . The structure of  claim 6  further comprising:
 a second doped region in the light-absorbing layer; and 
 a contact coupled to the second doped region. 
 
     
     
         11 . The structure of  claim 10  further comprising:
 a silicide layer on the second doped region, the silicide layer positioned between the contact and the second doped region. 
 
     
     
         12 . The structure of  claim 1  further comprising:
 a shallow trench isolation region in the semiconductor substrate, the shallow trench isolation region surrounding the portion of the semiconductor layer. 
 
     
     
         13 . The structure of  claim 1  further comprising:
 a shallow trench isolation region in the semiconductor substrate, 
 wherein the shallow trench isolation region surrounds an active device region of the semiconductor substrate, and the first doped region extends across an entirety of the active device region. 
 
     
     
         14 . The structure of  claim 1  wherein the dielectric liner is positioned between the conductor layer and the semiconductor layer. 
     
     
         15 . The structure of  claim 1  wherein the dielectric liner comprises silicon dioxide. 
     
     
         16 . The structure of  claim 1  wherein the conductor layer comprises doped polysilicon. 
     
     
         17 . The structure of  claim 1  wherein the conductor layer comprises a metal or a combination of polysilicon and metal. 
     
     
         18 . The structure of  claim 1  further comprising:
 a well in the semiconductor layer and the semiconductor substrate; and 
 a contact coupled by the well to the semiconductor substrate. 
 
     
     
         19 . The structure of  claim 1  wherein the semiconductor layer has a top surface, and the conductor layer provides a conductive path extending from the top surface of the semiconductor layer to the first doped region. 
     
     
         20 . A method comprising:
 forming a semiconductor layer on a top surface of a semiconductor substrate;   forming a doped region in the semiconductor substrate adjacent to the semiconductor layer; and   forming a deep trench isolation structure coupled to the doped region, wherein the deep trench isolation structure surrounds a portion of the semiconductor layer, and the deep trench isolation structure includes a dielectric liner and a conductor layer surrounded by the dielectric liner.