Semiconductor device

Abstract

Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a first transistor and a second transistor,   wherein one of a source and a drain of the first transistor is electrically connected to a gate electrode of the second transistor,   wherein the first transistor comprises a channel formation region in an oxide semiconductor layer,   wherein the oxide semiconductor layer comprises a crystal,   wherein a c-axis of the crystal of the oxide semiconductor layer is perpendicular to a surface of the oxide semiconductor layer,   wherein an off-state current of the first transistor is 1×10 −13  A or less,   wherein a potential is supplied to the gate electrode of the second transistor by turning on the first transistor, and   wherein the potential of the gate electrode of the second transistor is held by turning off the first transistor.   
     
     
         3 . The semiconductor device according to  claim 2 ,
 wherein no capacitor is provided to be electrically connected to the gate electrode of the second transistor.   
     
     
         4 . The semiconductor device according to  claim 2 , further comprising a capacitor electrically connected to the gate electrode of the second transistor. 
     
     
         5 . The semiconductor device according to  claim 2 ,
 wherein a hydrogen concentration measured by SIMS in the oxide semiconductor layer is  19  atoms/cm 3  or less.   
     
     
         6 . The semiconductor device according to  claim 2 ,
 wherein an off-state current per micrometer of a channel width of the first transistor is less than or equal to 10 zA/μm at 25° C.   
     
     
         7 . The semiconductor device according to  claim 2 ,
 wherein an off-state current per micrometer of a channel width of the first transistor is less than or equal to 100 zA/μm at 85° C.   
     
     
         8 . The semiconductor device according to  claim 2 ,
 wherein the off-state current of the first transistor is 1×10 13  A or less when a drain voltage is +1 V or +10 V and a gate voltage ranges from −20 V to −5 V.   
     
     
         9 . The semiconductor device according to  claim 2 ,
 wherein the oxide semiconductor layer comprises an In—Ga—Zn—O-based oxide semiconductor layer, an In—Sn—Zn—O-based oxide semiconductor layer, an In—Al—Zn—O-based oxide semiconductor layer, a Sn—Ga—Zn—O-based oxide semiconductor layer, an Al—Ga—Zn—O-based oxide semiconductor layer, a Sn—Al—Zn—O-based oxide semiconductor layer, an In—Zn—O-based oxide semiconductor layer, a Sn—Zn—O-based oxide semiconductor layer, an Al—Zn—O-based oxide semiconductor layer, an In—O-based oxide semiconductor layer, a Sn—O-based oxide semiconductor layer, or a Zn—O-based oxide semiconductor layer.   
     
     
         10 . The semiconductor device according to  claim 2 ,
 wherein the second transistor comprises a channel formation region in a silicon region.   
     
     
         11 . A memory cell comprising the semiconductor device according to  claim 2 . 
     
     
         12 . A memory cell array comprising the memory cell according to  claim 11 . 
     
     
         13 . A non-volatile memory comprising the memorycell according to  claim 11 . 
     
     
         14 . A semiconductor device comprising:
 a first transistor and a second transistor,   wherein one of a source and a drain of the first transistor is electrically connected to a gate electrode of the second transistor,   wherein the semiconductor device comprises a floating gate portion where the one of the source and the drain of the first transistor is electrically connected to the gate electrode of the second transistor,   wherein the first transistor comprises a channel formation region in an oxide semiconductor layer,   wherein the oxide semiconductor layer comprises a crystal,   wherein a c-axis of the crystal of the oxide semiconductor layer is perpendicular to a surface of the oxide semiconductor layer, and   wherein an off-state current of the first transistor is 1×10 13  A or less,   
     
     
         15 . The semiconductor device according to  claim 14 ,
 wherein no capacitor is provided to be electrically connected to the gate electrode of the second transistor.   
     
     
         16 . The semiconductor device according to  claim 14 , further comprising a capacitor electrically connected to the gate electrode of the second transistor. 
     
     
         17 . The semiconductor device according to  claim 14 ,
 wherein a hydrogen concentration measured by SIMS in the oxide semiconductor layer is 5×10 19  atoms/cm 3  or less.   
     
     
         18 . The semiconductor device according to  claim 14 ,
 wherein an off-state current per micrometer of a channel width of the first transistor is less than or equal to 10 zA/μm at 25° C.   
     
     
         19 . The semiconductor device according to  claim 14 ,
 wherein an off-state current per micrometer of a channel width of the first transistor is less than or equal to 100 zA/μm at 85° C.   
     
     
         20 . The semiconductor device according to  claim 14 ,
 wherein the off-state current of the first transistor is 1×10 13  A or less when a drain voltage is +1 V or +10 V and a gate voltage ranges from −20 V to −5 V.   
     
     
         21 . The semiconductor device according to  claim 14 ,
 wherein the oxide semiconductor layer comprises an In—Ga—Zn—O-based oxide semiconductor layer, an In—Sn—Zn—O-based oxide semiconductor layer, an In—Al—Zn—O-based oxide semiconductor layer, a Sn—Ga—Zn—O-based oxide semiconductor layer, an Al—Ga—Zn—O-based oxide semiconductor layer, a Sn—Al—Zn—O-based oxide semiconductor layer, an In—Zn—O-based oxide semiconductor layer, a Sn—Zn—O-based oxide semiconductor layer, an Al—Zn—O-based oxide semiconductor layer, an In—O-based oxide semiconductor layer, a Sn—O-based oxide semiconductor layer, or a Zn—O-based oxide semiconductor layer.   
     
     
         22 . The semiconductor device according to  claim 14 ,
 wherein the second transistor comprises a channel formation region in a silicon region.   
     
     
         23 . A memory cell comprising the semiconductor device according to  claim 14 . 
     
     
         24 . A memory cell array comprising the memory cell according to  claim 23 . 
     
     
         25 . A non-volatile memory comprising the memory cell according to claim 
     
     
         26 . A semiconductor device comprising:
 a first transistor and a second transistor,   wherein one of a source and a drain of the first transistor is electrically connected to a gate electrode of the second transistor,   wherein the first transistor comprises a channel formation region in an oxide semiconductor layer,   wherein the oxide semiconductor layer comprises a crystal,   wherein the oxide semiconductor layer comprises a region being an i-type or substantially i-type,   wherein a c-axis of the crystal of the oxide semiconductor layer is perpendicular to a surface of the oxide semiconductor layer,   wherein an off-state current of the first transistor is 1×10 13  A or less,   wherein a potential is supplied to the gate electrode of the second transistor by turning on the first transistor, and   wherein the potential of the gate electrode of the second transistor is held by turning off the first transistor.   
     
     
         27 . The semiconductor device according to  claim 26 ,
 wherein no capacitor is provided to be electrically connected to the gate electrode of the second transistor.   
     
     
         28 . The semiconductor device according to  claim 26 , further comprising a capacitor electrically connected to the gate electrode of the second transistor. 
     
     
         29 . The semiconductor device according to  claim 26 ,
 wherein a hydrogen concentration measured by SIMS in the oxide semiconductor layer is 5×10 19  atoms/cm 3  or less.   
     
     
         30 . The semiconductor device according to  claim 26 ,
 wherein an off-state current per micrometer of a channel width of the first transistor is less than or equal to 10 zA/μm at 25° C.   
     
     
         31 . The semiconductor device according to  claim 26 ,
 wherein an off-state current per micrometer of a channel width of the first transistor is less than or equal to 100 zA/μm at 85° C.   
     
     
         32 . The semiconductor device according to  claim 26 ,
 wherein the off-state current of the first transistor is 1×10 13  A or less when a drain voltage is +1 V or +10 V and a gate voltage ranges from −20 V to −5 V.   
     
     
         33 . The semiconductor device according to  claim 26 ,
 wherein the oxide semiconductor layer comprises an In—Ga—Zn—O-based oxide semiconductor layer, an In—Sn—Zn—O-based oxide semiconductor layer, an In—Al—Zn—O-based oxide semiconductor layer, a Sn—Ga—Zn—O-based oxide semiconductor layer, an Al—Ga—Zn—O-based oxide semiconductor layer, a Sn—Al—Zn—O-based oxide semiconductor layer, an In—Zn—O-based oxide semiconductor layer, a Sn—Zn—O-based oxide semiconductor layer, an Al—Zn—O-based oxide semiconductor layer, an In—O-based oxide semiconductor layer, a Sn—O-based oxide semiconductor layer, or a Zn—O-based oxide semiconductor layer.   
     
     
         34 . The semiconductor device according to  claim 26 ,
 wherein the second transistor comprises a channel formation region in a silicon region.   
     
     
         35 . A memory cell comprising the semiconductor device according to  claim 26 . 
     
     
         36 . A memory cell array comprising the memory cell according to  claim 35 . 
     
     
         37 . A non-volatile memory comprising the memory cell according to  claim 35 .