Semiconductor device structure including forksheet transistors and methods of forming the same

Abstract

A method for forming a semiconductor device structure includes forming first, second, and third fin structures from a substrate, wherein the first fin structure includes a first plurality of semiconductor layers, the second fin structure includes a second plurality of semiconductor layers, and the third fin structure includes a third plurality of semiconductor layers, and wherein each of the first, second, and third plurality of semiconductor layers comprises first semiconductor layers and second semiconductor layers. The method includes forming an insulating material between the first, second, and third fin structures, forming an end cut in the second fin structure, the end cut exposing an upper portion of the substrate, forming a dielectric fin in the end cut, forming a first dielectric feature on the insulating material and between the first fin structure and the dielectric fin, forming a second dielectric feature on the insulating material and between the dielectric fin structure and the third fin structure, forming a sacrificial gate stack on a portion of the first fin structure, the second fin structure, the third fin structure, the first dielectric feature, and the second dielectric feature, removing a portion of the first fin structure, the third fin structure, and the dielectric fin not covered by the sacrificial gate stack, removing the sacrificial gate stack to expose portions of the first, second, and third fin structures, removing the second semiconductor layers of the first, second, and third plurality of semiconductor layers, and forming a gate electrode layer to surround at least three surfaces of the first semiconductor layers of the first, second, and third plurality of semiconductor layers.

1 . A method for forming a semiconductor device structure, comprising:
 forming first, second, and third fin structures from a substrate, wherein the first fin structure includes a first plurality of semiconductor layers, the second fin structure includes a second plurality of semiconductor layers, and the third fin structure includes a third plurality of semiconductor layers, and wherein each of the first, second, and third plurality of semiconductor layers comprises first semiconductor layers and second semiconductor layers;   forming an insulating material between the first, second, and third fin structures;   forming an end cut in the second fin structure, the end cut exposing an upper portion of the substrate;   forming a dielectric fin in the end cut;   forming a first dielectric feature on the insulating material and between the first fin structure and the dielectric fin;   forming a second dielectric feature on the insulating material and between the dielectric fin structure and the third fin structure;   forming a sacrificial gate stack on a portion of the first fin structure, the second fin structure, the third fin structure, the first dielectric feature, and the second dielectric feature;   removing a portion of the first fin structure, the third fin structure, and the dielectric fin not covered by the sacrificial gate stack;   removing the sacrificial gate stack to expose portions of the first, second, and third fin structures;   removing the second semiconductor layers of the first, second, and third plurality of semiconductor layers; and   forming a gate electrode layer to surround at least three surfaces of the first semiconductor layers of the first, second, and third plurality of semiconductor layers.   
     
     
         2 . The method of  claim 1 , further comprising:
 after removing a portion of the first fin structure, the third fin structure, and the dielectric fin, forming a source/drain feature on the exposed portions of the first fin structure and the third fin structure not covered by the sacrificial gate stack.   
     
     
         3 . The method of  claim 2 , further comprising:
 forming an interlayer dielectric (ILD) layer over the first dielectric feature, the second dielectric feature, the dielectric fin, and the source/drain feature, so that at least portion of the first semiconductor layers of the second plurality of semiconductor layers are in contact with the ILD layer, and at least portion of the first semiconductor layers of the second plurality of semiconductor layers are in contact with the dielectric fin.   
     
     
         4 . The method of  claim 1 , wherein forming an end cut in the second fin structure comprises removing the second fin structure until a top of the substrate is exposed. 
     
     
         5 . The method of  claim 1 , wherein the end cut is formed by removing a top portion of the substrate such that an exposed top of the substrate is at a level below or slightly below an interface defined by the insulating material and the substrate. 
     
     
         6 . The method of  claim 5 , wherein removing a portion of the first fin structure, the third fin structure, and the dielectric fin not covered by the sacrificial gate stack is performed such that a top surface of the dielectric fin is at or below a top of the first and second dielectric features. 
     
     
         7 . A method for forming a semiconductor device structure, comprising:
 forming a fin structure from a substrate, the fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked;   forming a dielectric fin over the substrate, the dielectric fin being parallel to the fin structure;   forming an insulating material between the fin structure and the dielectric fin;   recessing the insulating material to expose the plurality of the first and second semiconductor layers and an upper portion of the dielectric fin;   forming a dielectric feature over the insulating material between the fin structure and the dielectric fin;   forming a sacrificial gate stack on a portion of the fin structure and the dielectric feature;   removing a portion of the fin structure and the dielectric fin not covered by the sacrificial gate stack;   forming a source/drain (S/D) feature on the fin structure;   forming a contact etch stop layer (CESL) on the S/D feature, the dielectric feature, and the dielectric fin;   forming an interlayer dielectric (ILD) layer on the CESL; and   removing the sacrificial gate stack and the second semiconductor layers.   
     
     
         8 . The method of  claim 7 , wherein removing a portion of the fin structure and the dielectric fin not covered by the sacrificial gate stack is performed such that a top surface of the dielectric fin is at a level below a top surface of a topmost first semiconductor layer. 
     
     
         9 . The method of  claim 8 , wherein the S/D feature is formed to have a contact surface covering each of the plurality of the first semiconductor layers. 
     
     
         10 . The method of  claim 8 , wherein the dielectric fin is formed to have a contact surface that is free from contacting the topmost first semiconductor layer. 
     
     
         11 . The method of  claim 7 , wherein the CESL over the dielectric fin is formed to have a top surface at a level below a top surface of a topmost first semiconductor layer. 
     
     
         12 . The method of  claim 11 , wherein the CESL is formed to have a portion in contact with the top surface and a sidewall of the dielectric fin. 
     
     
         13 . The method of  claim 7 , further comprising:
 forming a gate electrode layer to surround at least three surfaces of each of the first semiconductor layers.   
     
     
         14 . The method of  claim 7 , wherein forming a dielectric feature further comprises:
 forming a first dielectric layer in contact with at least the insulating material, the first and second semiconductor layers, and the dielectric fin;   forming a second dielectric layer on the first dielectric layer; and   forming a third dielectric layer on the second dielectric layer, wherein the first and third dielectric layers comprise a material chemically different than the second dielectric layer.   
     
     
         15 . The method of  claim 14 , wherein the first dielectric layer is in contact with the dielectric fin. 
     
     
         16 . The method of  claim 15 , wherein the second dielectric layer is in contact with the CESL. 
     
     
         17 . A method for forming a semiconductor device structure, comprising:
 forming a fin structure from a substrate, the fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked, each first and second semiconductor layer extending along a first direction;   forming a first dielectric feature on the substrate, the first dielectric feature extending along a second direction perpendicular to the first direction;   forming a second dielectric feature over the substrate, the second dielectric feature extending along the section direction;   forming a sacrificial gate stack on a portion of the fin structure and the first dielectric feature;   removing the plurality of first and second semiconductor layers not covered by the sacrificial gate stack to expose the substrate;   forming a source/drain (S/D) feature on the exposed substrate;   forming a contact etch stop layer (CESL) on exposed surfaces of the S/D feature and the first dielectric feature;   forming an interlayer dielectric (ILD) layer on the CESL;   removing the sacrificial gate stack and the second semiconductor layers; and   forming a gate electrode layer to surround at least three surfaces of each of the first semiconductor layers.   
     
     
         18 . The method of  claim 17 , wherein the first dielectric feature and the second dielectric feature are separated from each other by the CESL and the ILD. 
     
     
         19 . The method of  claim 18 , wherein the second dielectric feature, the CESL, and the ILD are in contact with each of the first semiconductor layers. 
     
     
         20 . The method of  claim 18 , wherein the S/D feature is formed such that a sidewall of the S/D feature is in contact with the first dielectric feature.