Method for fabricating semiconductor interconnect structure and semiconductor structure thereof

Abstract

A semiconductor interconnect structure and a fabricating method thereof are disclosed. The semiconductor interconnect structure includes a stacked structure including bonded multiple layers of wafer or die, through silicon vias (TSVs) penetrating the bonded multiple layers of wafer or die of the stacked structure and a dielectric isolation layer disposed on the inner surface of the TSVs. Each layer of wafer or die includes a substrate and a wiring layer, and the wiring layer is composed of metal wires. The dielectric isolation layer exposes end surfaces of the multiple metal wires.

1 . A semiconductor interconnect structure, comprising:
 a stacked structure comprising bonded a plurality of layers of wafer or die, each layer of wafer or die comprising a substrate and a wiring layer, and the wiring layer comprising a plurality of metal wires;   at least one through silicon via (TSV) penetrating the bonded plurality of layers of wafer or die of the stacked structure, a center of a penetration position on each layer of wafer or die being disposed between adjacent metal wires, and a sidewall of the TSV intersecting with the plurality of metal wires, and   a dielectric isolation layer disposed on an inner surface of the at least one TSV and exposing end surfaces of the plurality of metal wires.   
     
     
         2 . The semiconductor interconnect structure of  claim 1 , wherein the TSV has a cross-sectional top view of a circle shape, a polygon shape, or an irregular shape. 
     
     
         3 . The semiconductor interconnect structure of  claim 1 , wherein the TSV via penetrating the bonded plurality of layers of wafer or die is a one-piece structure formed integrally. 
     
     
         4 . The semiconductor interconnect structure of  claim 1 , wherein the TSV penetrating the bonded plurality of layers of wafer or die comprises no bumps among the bonded plurality of layers of wafer or die. 
     
     
         5 . The semiconductor interconnect structure of  claim 1 , wherein a difference between a diameter of the TSV and a space between the adjacent metal wires is within a preset safe range. 
     
     
         6 . The semiconductor interconnect structure of  claim 5 , wherein the diameter of the TSV is consistent in each of the bonded plurality of layers of wafer or die. 
     
     
         7 . The semiconductor interconnect structure of  claim 1 , wherein a seed metal is sputtered on the dielectric isolation layer and the exposed end surfaces of the plurality of metal wires, and the seed metal comprises tantalum or copper. 
     
     
         8 . The semiconductor interconnect structure of  claim 1 , wherein the TSV is filled with a conductive metal, and the conductive metal comprises copper.