Systems and Methods for Reducing Standby Power in Floating Body Memory Devices

Abstract

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor memory array configured for reducing standby power, said array comprising:
 a plurality of floating body memory cells each having at least two stable floating body charge levels, wherein said floating body charge levels are maintained by a vertical bipolar holding mechanism;   wherein said semiconductor memory array comprises at least two back-bias regions that can be independently controlled; and   means for periodically turning off and on said vertical bipolar holding mechanism to reduce standby power of said floating body memory cells.   
     
     
         22 . The semiconductor memory array of  claim 21 , wherein each of said plurality of floating body memory cells further comprises a floating body region having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type. 
     
     
         23 . The semiconductor memory array of  claim 22 , wherein said at least two back-bias regions have a second conductivity type selected from said p-type conductivity type and said n-type conductivity type, wherein said second conductivity type is different from said first conductivity type. 
     
     
         24 . The semiconductor memory array of  claim 21 , wherein applying a back-bias to said at least two back-bias regions results in maintenance of said stable floating body charge levels. 
     
     
         25 . The semiconductor memory array of  claim 24 , wherein said back-bias is a constant positive voltage bias. 
     
     
         26 . The semiconductor memory array of  claim 24 , wherein said back-bias is a periodic pulse of positive voltage. 
     
     
         27 . The semiconductor memory array of  claim 21 , further comprising at least one reference cell to determine a period for said periodically turning off and on said vertical bipolar holding mechanism. 
     
     
         28 . The semiconductor memory array of  claim 27 , further comprising level detectors to determine said stable floating body charge levels. 
     
     
         29 . The semiconductor memory array of  claim 21 , further comprising equalizing transistors connecting said at least two back-bias regions. 
     
     
         30 . A system for reducing standby power, said system comprising:
 a plurality of floating body memory cells each having at least two stable floating body charge levels, wherein said stable floating body charge levels are maintained by a vertical bipolar holding mechanism;   at least two back-bias regions that can be independently controlled; and   a controller configured to periodically turn off and on said vertical bipolar holding mechanism to reduce standby power of said floating body memory cells.   
     
     
         31 . The system of  claim 30 , wherein each of said plurality of floating body memory cells further comprises a floating body region having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type. 
     
     
         32 . The system of  claim 31 , wherein said at least two back-bias regions have a second conductivity type selected from said p-type conductivity type and said n-type conductivity type, wherein said second conductivity type is different from said first conductivity type. 
     
     
         33 . The system of  claim 30 , wherein applying a back-bias to said at least two back-bias region results in maintenance of said stable floating body charge levels. 
     
     
         34 . The system of  claim 33 , wherein said back-bias is a constant positive voltage bias. 
     
     
         35 . The system of  claim 33 , wherein said back-bias is a periodic pulse of positive voltage. 
     
     
         36 . The system of  claim 30 , further comprising at least one reference cell to determine a period for said periodically turning off and on said vertical bipolar holding mechanism. 
     
     
         37 . The system of  claim 36 , further comprising level detectors to determine said floating body charge levels. 
     
     
         38 . The system of  claim 30 , further comprising equalizing transistors connecting said at least two back-bias regions.