Write disturb mitigation for non-linear polar material based multi-capacitor bit-cell

Abstract

A disturb mitigation scheme is described for a 1TnC or multi-element ferroelectric gain bit-cell where after writing to a selected capacitor of the bit-cell, a cure phase is initiated. Between the cure phase and the write phase, there may be zero or more cycles where the selected word-line, bit-line, and plate-lines are pulled-down to ground. The cure phase may occur immediately before the write phase. In the cure phase, the word-line is asserted again just like in the write phase. In the cure phase, the voltage on bit-line is inverted compared to the voltage on the bit-line in the write phase. By programming a value in a selected capacitor to be opposite of the value written in the write phase of that selected capacitor, time accumulation of disturb is negated. This allows to substantially zero out disturb field on the unselected capacitors of the same bit-cell and/or other unselected bit-cells.

We claim: 
     
         1 . An apparatus comprising:
 a transistor having a gate terminal coupled to a word-line, a source terminal couple to a bit-line, and a drain terminal coupled to a storage node;   a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line; and   a circuitry to perform a first write operation during a first phase on a selected capacitor of the plurality of capacitors, wherein the circuitry is to perform a second write operation during a second phase, wherein the second write operation mitigates write disturb effects on unselected capacitors of the plurality of capacitors.   
     
     
         2 . The apparatus of  claim 1 , wherein second write operation is complementary or inverted form of the first write operation. 
     
     
         3 . The apparatus of  claim 1 , wherein the first write operation and the second write operation are separated by zero or more cycles where the word-line, the bit-line, and the individual plate-line are pulled to ground. 
     
     
         4 . The apparatus of  claim 1 , wherein the first phase is before the second phase. 
     
     
         5 . The apparatus of  claim 1 , wherein the second phase is before the first phase. 
     
     
         6 . The apparatus of  claim 1 , wherein the word-line is boosted in the first phase and the second phase. 
     
     
         7 . The apparatus of  claim 1 , wherein a plate-line, in the second phase, coupled to the selected capacitor is set to substantially half of a voltage on a power supply rail. 
     
     
         8 . The apparatus of  claim 7 , wherein the plate-line of the selected capacitor is pulsed to the voltage on the power supply rail in the first phase to program the selected capacitor. 
     
     
         9 . The apparatus of  claim 1 , wherein the individual plate-line coupled to the individual capacitor is set to substantially half of a voltage on a power supply rail in the second phase. 
     
     
         10 . The apparatus of  claim 1 , wherein the individual capacitor includes a top electrode which is coupled to the individual plate-line. 
     
     
         11 . The apparatus of  claim 10 , wherein the top electrode is coupled to the individual plate-line using a pedestal. 
     
     
         12 . The apparatus of  claim 1 , wherein the individual capacitor includes:
 a first layer coupled to a bottom electrode which is coupled to the storage node, wherein the first layer comprises a first refractive inter-metallic material;   a second layer on the first layer, wherein the second layer comprises a first conductive oxide;   a third layer comprising non-linear polar material, wherein the third layer is on the second layer;   a fourth layer on the third layer, wherein the fourth layer comprises a second conductive oxide; and   a fifth layer on the fourth layer, wherein the fifth layer comprises a second refractive inter-metallic material, wherein the individual plate-line is coupled to the fifth layer.   
     
     
         13 . The apparatus of  claim 12 , wherein:
 the first refractive inter-metallic material and the second refractive inter-metallic material include one or more of Ta, Ti, Al, W, Ni, Ga, Mn, Fe, B, C, N or Co; and   the first conductive oxide and the second conductive oxide include one or more of: Ir, In, Fe, Ru, Pd, Os, or Re, wherein the apparatus comprises a sixth layer adjacent to side walls of the first layer, the second layer, the third layer, and the fourth layer, wherein the sixth layer includes one of: Ti—Al—O, Al2O3, or MgO.   
     
     
         14 . The apparatus of  claim 1 , wherein the individual capacitor includes:
 a first layer coupled to a bottom electrode which is coupled to the storage node, wherein the first layer comprises a first conductive oxide;   a second layer comprising non-linear polar material, wherein the second layer is on the first layer; and   a third layer on the second layer, wherein the third layer comprises a second conductive oxide, wherein the individual plate-line is coupled to the third layer.   
     
     
         15 . The apparatus of  claim 1 , wherein the individual plate-line is parallel to the word-line. 
     
     
         16 . The apparatus of  claim 1 , wherein the plurality of capacitors comprises non-linear polar material. 
     
     
         17 . The apparatus of  claim 16 , wherein the non-linear polar material includes one of:
 Bismuth ferrite (BFO), BFO with a doping material wherein the doping material is one of Lanthanum, or elements from lanthanide series of periodic table;   Lead zirconium titanate (PZT), or PZT with a doping material, wherein the doping material is one of La or Nb;   a relaxor ferroelectric which includes one of lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), Barium Titanium-Bismuth Zinc Niobium Tantalum (BT-BZNT), or Barium Titanium-Barium Strontium Titanium (BT-BST);   a perovskite which includes one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3;   a hexagonal ferroelectric which includes one of: YMnO3, or LuFeO3;   hexagonal ferroelectrics of a type h-RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);   Hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides;   Hafnium oxides as Hf1-x Ex Oy, where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y;   Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N or Al(1-x-y)Mg(x)Nb(y)N, y doped HfO2, where x includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein ‘x’ is a fraction;   Niobate type compounds LiNbO3, LiTaO3, Lithium iron Tantalum Oxy Fluoride, Barium Strontium Niobate, Sodium Barium Niobate, or Potassium strontium niobate; or   an improper ferroelectric which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 to 100.   
     
     
         18 . An apparatus comprising:
 a first transistor having a first gate terminal coupled to a word-line, a first source terminal couple to a bit-line, and a first drain terminal coupled to a storage node;   a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal couple to a sense line, and a second drain terminal coupled to a bias;   a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line; and   a circuitry to perform a first write operation during a first phase on a selected capacitor of the plurality of capacitors, wherein the circuitry is to perform a second write operation during a second phase, and wherein second write operation is complementary or inverted form of the first write operation.   
     
     
         19 . The apparatus of  claim 18 , wherein the first write operation and the second write operation are separated by zero or more cycles where the word-line, the bit-line, and the individual plate-line are pulled to ground. 
     
     
         20 . A system comprising:
 a processor circuitry to execute one or more instructions;   a memory circuitry to store the one or more instructions; and   a communication interface to allow the processor circuitry to communicate with another device, wherein the memory circuitry includes a plurality of bit-cells organized in a memory array, wherein an individual bit-cell of the plurality of bit-cells includes:   a transistor having a gate terminal coupled to a word-line, a source terminal couple to a bit-line, and a drain terminal coupled to a storage node;   a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line; and   a circuitry to perform a first write operation during a first phase on a selected capacitor of the plurality of capacitors, wherein the circuitry is to perform a second write operation during a second phase, wherein the second write operation mitigates write disturb effects on unselected capacitors of the plurality of capacitors.