Wear leveling in solid state drives

Abstract

A computer storage device having: a host interface; a controller; non-volatile storage media having memory units of different types and having different program erase budgets; and firmware. The firmware instructs the controller to: generate an address map mapping logical addresses to physical addresses of the memory units the different types; and adjust the address map based at least in part on the program erase budgets to level wear across the memory units of the different types.

What is claimed is: 
     
         1 . A device, comprising:
 a set of non-volatile memory units of different types that have different program erase budgets corresponding to the different types respectively; and   a controller configured to:
 access the memory units using an address map that maps logical addresses to physical addresses of the memory units; 
 track degrees of wear of the memory units based on a normalized degree of wear for each of the memory units of different types; and 
 adjust the address map based at least in part on the normalized degree of wear for at least one of the memory units. 
   
     
     
         2 . The device of  claim 1 , further comprising a host interface configured to communicate with a host device through a communication channel connecting the host interface and the host device. 
     
     
         3 . The device of  claim 1 , wherein the controller is further configured to generate the address map prior to the access of the memory units using the address map. 
     
     
         4 . The device of  claim 1 , wherein the normalized degree of wear accounts for differences in the program erase budgets corresponding to the different types. 
     
     
         5 . The device of  claim 1 , wherein the degrees of wear are normalized using a largest one of the program erase budgets corresponding to the different types. 
     
     
         6 . The device of  claim 1 , wherein the controller is further configured to track the degrees of wear by tracking numbers of normalized program erase cycles of the memory units, wherein the numbers of normalized program erase cycles of the memory units are proportional to a number of actual program erase cycles of the memory units and inversely proportional to program erase budgets of the memory units. 
     
     
         7 . The device of  claim 1 , wherein the non-volatile memory units of different types comprise at least two of:
 single level cell flash memory;   multi level cell flash memory;   triple level cell flash memory; and   quad level cell flash memory.   
     
     
         8 . The device of  claim 1 , wherein the controller is further configured to:
 receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit; and   identify, based on the normalized degree of wear for at least two of the memory units, a second memory unit having less wear than the first memory unit.   
     
     
         9 . The device of  claim 8 , wherein the controller is further configured to:
 change the address map to map the logical address to the second memory unit; and   write the data in the second memory unit.   
     
     
         10 . The device of  claim 9 , wherein the first memory unit and the second memory unit are of different types. 
     
     
         11 . The device of  claim 9 , wherein the first memory unit and the second memory unit have different program erase budgets. 
     
     
         12 . A non-transitory computer storage medium storing instructions thereon which, upon execution by a controller of a memory device, cause the memory device to:
 access memory units using an address map that maps logical addresses to physical addresses of the memory units, wherein the memory units comprise a set of memory units of different types that have different program erase budgets corresponding to the different types respectively;   track degrees of wear of the memory units based on a normalized degree of wear for each of the memory units of different types; and   adjust the address map based at least in part on the normalized degree of wear for at least one of the memory units.   
     
     
         13 . The non-transitory computer storage medium of  claim 12 , wherein the instructions further cause the memory device to communicate with a host device through a communication channel connecting the host interface and the host device. 
     
     
         14 . The non-transitory computer storage medium of  claim 12 , generate the address map prior to the access of the memory units using the address map. 
     
     
         15 . The non-transitory computer storage medium of  claim 12 , wherein the instructions further cause the memory device to:
 receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit;   identify, based on the normalized degree of wear for at least two of the memory units, a second memory unit having less wear than the first memory unit;   receive a request to write data in a logical address that is currently mapped by the address map to a first memory unit; and   identify, based on the normalized degree of wear for at least two of the memory units, a second memory unit having less wear than the first memory unit.   
     
     
         16 . The non-transitory computer storage medium of  claim 12 , wherein the degrees of wear are normalized using a largest one of the program erase budgets corresponding to the different types. 
     
     
         17 . The non-transitory computer storage medium of  claim 12 , wherein the memory units of different types comprise at least two of:
 single level cell non-volatile flash memory;   multi level cell non-volatile flash memory;   triple level cell non-volatile flash memory; and   quad level cell non-volatile flash memory.   
     
     
         18 . A method comprising:
 accessing, by a controller of a memory device, memory units using an address map that maps logical addresses to physical addresses of the memory units, wherein the memory units comprise a set of memory units of different types;   tracking, by the controller, degrees of wear of the memory units based on a normalized degree of wear for each of the memory units; and   adjusting, by the controller, the address map based at least in part on the normalized degree of wear for at least one of the memory units.   
     
     
         19 . The method of  claim 18 , wherein the degrees of wear are normalized using a largest one of the program erase budgets of the memory units. 
     
     
         20 . The method of  claim 18 , wherein the memory units comprise at least two memory units of different types, wherein the different types of memory units have different program eras budgets.