Semiconductor memory device and method of forming the same

Abstract

A semiconductor device includes a substrate with a metal line embedded in the substrate, a dielectric layer disposed on the substrate, a bottom electrode via extending through the dielectric layer and landing on a top surface of the metal line, a bottom electrode disposed on a top surface of the bottom electrode via, a magnetic tunneling junction stack disposed on a top surface of the bottom electrode, and a top electrode disposed on the magnetic tunneling junction stack. A lower portion of the bottom electrode via includes a first metal, and an upper portion of the bottom electrode via includes a second metal that is different from the first metal.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate with a metal line embedded in the substrate;   a dielectric layer disposed on the substrate;   a bottom electrode via extending through the dielectric layer and landing on a top surface of the metal line, wherein a lower portion of the bottom electrode via includes a first metal, and an upper portion of the bottom electrode via includes a second metal that is different from the first metal;   a bottom electrode disposed on a top surface of the bottom electrode via;   a magnetic tunneling junction stack disposed on a top surface of the bottom electrode; and   a top electrode disposed on the magnetic tunneling junction stack.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the bottom electrode via includes a diffusion barrier layer covering at least sidewalls of the upper portion of the bottom electrode via. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the first metal has a lower resistivity than the second metal. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the first metal has a first thickness, and the second metal has a second thickness that is smaller than the first thickness. 
     
     
         5 . The semiconductor device of  claim 4 , wherein a ratio of the first thickness over the second thickness ranges from about 2:1 to about 5:1. 
     
     
         6 . The semiconductor device of  claim 4 , wherein the second thickness is not less than about 120 Å. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the first metal is copper, and the second metal is tungsten. 
     
     
         8 . The semiconductor device of  claim 1 , wherein a portion of a top surface of the dielectric layer is below the top surface of the bottom electrode via. 
     
     
         9 . The semiconductor device of  claim 8 , wherein the portion of the top surface of the dielectric layer is above an interface between the first metal and the second metal. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the portion of the top surface of the dielectric layer is above the interface for at least 30 Å. 
     
     
         11 . A memory device, comprising:
 a bottom electrode via including a lower portion and an upper portion, wherein the lower portion includes a first metal, and the upper portion includes a second metal that is different than the first metal;   a bottom electrode disposed on the bottom electrode via;   a magnetic tunneling junction stack disposed on the bottom electrode, wherein the magnetic tunneling junction stack includes a lower ferromagnetic layer, a tunneling barrier layer over the lower ferromagnetic layer, and an upper ferromagnetic layer over the tunneling barrier layer; and   a top electrode disposed on the magnetic tunneling junction stack.   
     
     
         12 . The memory device of  claim 11 , wherein the first metal has a lower resistivity than the second metal. 
     
     
         13 . The memory device of  claim 11 , wherein the first metal is copper, and the second metal is tungsten. 
     
     
         14 . The memory device of  claim 11 , wherein a thickness of the second metal is smaller than that of the first metal. 
     
     
         15 . The memory device of  claim 11 , further comprising:
 a dielectric layer surrounding the bottom electrode via, wherein a portion of the dielectric layer is directly under and in physical contact with a bottom surface of the bottom electrode.   
     
     
         16 . The memory device of  claim 11 , wherein a top surface of the second metal has a concave profile. 
     
     
         17 . A semiconductor device, comprising:
 a dielectric layer over a substrate;   a bottom electrode via through the dielectric layer, wherein the bottom electrode via includes a first metal layer, a second metal layer above the first metal layer, and a barrier layer in physical contact with sidewalls of the first metal layer and the second metal layer, the first metal layer is essentially of copper, and the second metal layer is essentially of tungsten;   a bottom electrode over the bottom electrode via;   a magnetic tunneling junction stack over the bottom electrode; and   a top electrode over the magnetic tunneling junction stack.   
     
     
         18 . The semiconductor device of  claim 17 , wherein a ratio of a thickness of the first metal layer over a thickness of the second metal layer ranges from about 2:1 to about 5:1. 
     
     
         19 . The semiconductor device of  claim 17 , wherein a top surface of the dielectric layer has a step profile, such that a first portion of the top surface of the dielectric layer is in physical contact with a bottom surface of the bottom electrode, and a second portion of the top surface of the dielectric layer is below a top surface of the second metal layer. 
     
     
         20 . The semiconductor device of  claim 17 , further comprising:
 a sidewall spacer layer on sidewalls of the magnetic tunneling junction stack and the bottom electrode, wherein a bottom surface of the sidewall spacer layer is below a top surface of the second metal layer and above an interface between the first and second metal layers; and   a top electrode via over the top electrode.