Memory chiplet having multiple arrays of memory devices and methods of forming the same

Abstract

A disclosed memory structure includes a first memory region including a first memory array of SRAM memory devices, a second memory region including a second memory array of 1T1C memory devices, and a third memory region including a third memory array of FeFET memory devices. The memory structure further includes at least one data bus laterally extending across the first memory region, the second memory region, and third memory region and configured to provide data transfer among the first memory array, the second memory array, and the third memory array. The memory structure further includes a plurality of peripheral circuit devices formed at a semiconductor material layer of the memory structure, the peripheral circuit devices configured to control the first memory array, the second memory array, and the third memory array. At least one of the second memory array and the third memory array may be a 3-dimensional memory array.

What is claimed is: 
     
         1 . A method of fabricating a memory structure, comprising:
 forming a first memory array located in a first memory region of a die, the first memory array comprising an array of SRAM memory devices;   forming a second memory array located in a second memory region of the die, the second memory array comprising an array of 1T1C memory devices;   forming a third memory array located in a third memory region of the die, the third memory region comprising an array of FeFET memory devices;   forming at least one data bus laterally extending across the first memory region, the second memory region, and third memory region and configured to provide data transfer among the first memory array, the second memory array, and the third memory array; and   forming peripheral circuit devices at a semiconductor material layer of the die, the peripheral circuit devices configured to control the first memory array, the second memory array, and the third memory array.   
     
     
         2 . The method of  claim 1 , wherein:
 forming the at least one data bus further comprises forming a plurality of interconnect level structures;   forming the first memory array further comprises forming the SRAM memory devices on the semiconductor material layer of the die;   forming the second memory array further comprises forming the 1T1C memory devices over a first interconnect level structure of the plurality of interconnect level structures;   forming the third memory array further comprises forming the FeFET memory devices over a second interconnect level structure of the plurality of interconnect level structures; and   forming the peripheral circuit devices further comprises configuring the peripheral circuit devices to provide control access across array boundaries.   
     
     
         3 . The method of  claim 1 , wherein the peripheral circuit devices comprise sense amplifiers and decoder circuits for the one or more of the respective first memory array, the second memory array, and the third memory array. 
     
     
         4 . The method of  claim 3 , wherein forming the peripheral circuit devices further comprises forming data bus switching devices that are configured to control data transfer between the first memory array, the second memory array, and the third memory array. 
     
     
         5 . The method of  claim 3 , wherein forming the peripheral circuit devices further comprises forming thin film transistor devices located at one or both of a first interconnect level and a second interconnect level. 
     
     
         6 . The method of  claim 1 , further comprising:
 forming computing logic devices located on the semiconductor material layer of the die,   wherein forming the at least one data bus further comprises coupling the computing logic devices to the first memory array, the second memory array, the third memory array, and the peripheral circuit devices.   
     
     
         7 . The method of  claim 1 , further comprising forming one or more of the second memory array and the third memory array as a 3-dimensional memory array including word lines that are shared between two or more stacked active device layers within the 3-dimensional memory array. 
     
     
         8 . A method of controlling a memory structure, comprising:
 receiving and storing data to a first memory array located in a first memory region of a die, the first memory region comprising an array of SRAM memory devices;   transferring data from the first memory array to a second memory array located in a second memory region of the die, the second memory region comprising an array of 1T1C memory devices; and   transferring data from the first memory array and/or from the second memory array to a third memory array located in a third memory region of the die, the third memory region comprising an array of FeFET memory devices,
 wherein the data is transferred among the first memory array, the second memory array, and the third memory array via at least one data bus laterally extending across the first memory region, the second memory region, and third memory region, and 
 wherein the transfer of data among the first memory array, the second memory array, and the third memory array is controlled by peripheral circuit devices formed at a semiconductor material layer of the memory structure. 
   
     
     
         9 . The method of  claim 8 , wherein transferring data among the first memory array, the second memory array, and the third memory array further comprises:
 controlling data bus switching devices to control common bit lines that are switchably shared between the first memory array, the second memory array, and the third memory array to thereby transmit data among the first memory array, the second memory array, and the third memory array via the common bit lines.   
     
     
         10 . The method of  claim 8 , wherein transferring data among the first memory array, the second memory array, and the third memory array further comprises:
 controlling word lines that are formed as lateral interconnect structures that couple memory devices in a plurality of active device layers.   
     
     
         11 . The method of  claim 8 , wherein transferring data among the first memory array, the second memory array, and the third memory array further comprises:
 controlling peripheral devices formed as thin film transistor devices located in the second memory region and the third memory region.   
     
     
         12 . A method of forming a memory structure, comprising:
 forming a first memory region at a semiconductor material layer of a die;   forming a second memory region over the first memory region; and   forming a third memory region over the first memory region,   wherein the first memory region, the second memory region, and the third memory region are all formed on a single die.   
     
     
         13 . The method of  claim 12 , further comprising:
 forming a first interconnect level structure over the first memory region prior to forming the second memory region such that the first interconnect level structure separates the second memory region from the first memory region; and   forming a second interconnect level structure over the second memory region prior to forming the third memory region such that the second interconnect level structure separates the second memory region from the third memory region.   
     
     
         14 . The method of  claim 12 , further comprising:
 forming at least one data bus that is laterally extending across the first memory region, the second memory region, and the third memory region; and   electrically connecting the at least one data bus to the first memory region, the second memory region, and the third memory region.   
     
     
         15 . The method of  claim 14 , wherein forming the at least one data bus further comprises:
 forming the at least one data bus to comprises common bit lines that are switchably shared between the first memory region, the second memory region, and the third memory region such that the at least one data bus is configured to switchably transfer data among the first memory region, the second memory region, and the third memory region.   
     
     
         16 . The method of  claim 12 , further comprising:
 forming peripheral circuit devices at the semiconductor material layer; and   electrically connecting the peripheral circuit devices to the first memory region, the second memory region, and the third memory region,
 wherein forming the peripheral circuit devices at the semiconductor material layer further comprises forming the peripheral circuit devices to be located beneath the second memory region and beneath the third memory region. 
   
     
     
         17 . The method of  claim 16 , further comprising:
 forming additional peripheral devices as thin film transistor devices including sense amplifiers and decoder circuits located in at least one of the second memory region and the third memory region.   
     
     
         18 . The method of  claim 12 , wherein:
 forming the first memory region further comprises forming a first memory array of volatile memory devices;   forming the second memory region further comprises forming a second memory array of non-volatile memory devices; and   forming the third memory region further comprises forming a third memory array configured as a 3-dimensional memory array comprising word lines that are shared between a plurality of stacked active device layers within the 3-dimensional memory array.   
     
     
         19 . The method of  claim 18 , wherein:
 forming the first memory region further comprises forming a first memory array of SRAM memory devices;   forming the second memory region further comprises forming a second memory array of 1T1C memory devices; and   forming the third memory region further comprises forming a third memory array of FeFET memory devices.   
     
     
         20 . The method of  claim 18 , wherein forming the third memory region further comprises:
 forming the word lines as vertical interconnect structures that couple memory devices of the 3-dimensional memory array that comprises the plurality of stacked active device layers.