Semiconductor device and method of fabricating the same

Abstract

A semiconductor includes a ferroelectric layer, a first semiconductor layer, a first gate, a second semiconductor layer, a second gate and contact structures. The ferroelectric layer has a first surface and a second surface opposite to the first surface. The first semiconductor layer is disposed on the first surface of the ferroelectric layer. The first gate is disposed on the first semiconductor layer over the first surface. The second semiconductor layer is disposed on the second surface of the ferroelectric layer. The second gate is disposed on the second semiconductor layer over the second surface. The contacts structures are connected to the first semiconductor layer and the second semiconductor layer.

What is claimed is: 
     
         1 . A device, comprising:
 a ferroelectric layer;   a first channel layer and a second channel layer disposed on two opposing sides of the ferroelectric layer and contacting the ferroelectric layer; and   gate electrodes disposed on two opposing sides of the ferroelectric layer and over the first channel layer and the second channel layer.   
     
     
         2 . The device according to  claim 1 , wherein a lateral dimension of the first channel layer is different from a lateral dimension of the second channel layer. 
     
     
         3 . The device according to  claim 1 , wherein a lateral dimension of the first channel layer is equal to a lateral dimension of the second channel layer. 
     
     
         4 . The device according to  claim 1 , further comprising:
 first source and drain contacts connected to a first side of the first channel layer, wherein the first side of the first channel layer is facing the ferroelectric layer; and   second source and drain contacts connected to a first side of the second channel layer, wherein the first side of the second channel layer is facing away from the ferroelectric layer.   
     
     
         5 . The device according to  claim 4 , wherein the first source and drain contacts are located on two sides of the second source and drain contacts. 
     
     
         6 . The device according to  claim 1 , further comprising a first gate dielectric and a second gate dielectric disposed on two opposing sides of the ferroelectric layer, and respectively disposed on the first channel layer and the second channel layer. 
     
     
         7 . The device according to  claim 1 , wherein sidewalls of the ferroelectric layer are misaligned with sidewalls of the first channel layer and sidewalls of the second channel layer. 
     
     
         8 . A structure, comprising:
 a first transistor comprising a first semiconductor layer, a first gate dielectric and a first gate electrode sequentially stacked up along a first direction;
 a second transistor comprising a second semiconductor layer, a second gate dielectric and a second gate electrode sequentially stacked up along a second direction, wherein the second direction is opposite to the first direction; and 
 a ferroelectric layer shared between the first transistor and the second transistor. 
   
     
     
         9 . The structure according to  claim 8 , wherein the ferroelectric layer is sandwiched in between the first semiconductor layer and the second semiconductor layer. 
     
     
         10 . The structure according to  claim 8 , wherein sidewalls of the first gate dielectric extend beyond sidewalls of the first gate electrode, and sidewalls of the second gate dielectric is aligned with sidewalls of the second gate dielectric. 
     
     
         11 . The structure according to  claim 8 , further comprising an interlayer dielectric layer covering the first semiconductor layer, the ferroelectric layer, the second semiconductor layer and the second gate electrode. 
     
     
         12 . The structure according to  claim 8 , wherein sidewalls of the ferroelectric layer are aligned with sidewalls of the first gate electrode and sidewalls of the second gate electrode. 
     
     
         13 . The structure according to  claim 8 , further comprising:
 first source and drain contacts connected to a top surface of the first semiconductor layer; and   second source and drain contacts connected to a top surface of the second semiconductor layer.   
     
     
         14 . The structure according to  claim 13 , wherein the ferroelectric layer is directly contacting the top surface of the first semiconductor layer, and directly contacting a bottom surface of the ferroelectric layer. 
     
     
         15 . A structure, comprising:
 a substrate;   a first gate structure, a first channel layer, an insulating layer, a second channel layer and a second gate structure stacked up in sequence along a build-up direction over the substrate;   an interlayer dielectric layer formed over the substrate and laterally surrounding the first channel layer, the insulating layer, the second channel layer and the second gate structure; and
 contact structures extending from a top surface of the interlayer dielectric layer towards a top surface of the first channel layer and towards a top surface of the second channel layer. 
   
     
     
         16 . The structure according to  claim 15 , wherein the insulating layer is a single crystalline material. 
     
     
         17 . The structure according to  claim 15 , wherein sidewalls of the insulating layer are aligned with sidewalls of the second channel layer, and misaligned with sidewalls of the first channel layer. 
     
     
         18 . The structure according to  claim 15 , wherein the contact structures comprise:
 first source and drain contacts connected to the top surface of the first channel layer; and   second source and drain contacts connected to the top surface of the second channel layer, wherein a total length of the first source and drain contacts is different from a total length of the second source and drain contacts.   
     
     
         19 . The structure according to  claim 15 , further comprising:
 a first gate dielectric sandwiched between the first gate structure and the first channel layer; and   a second gate dielectric sandwiched between the second gate structure and the second channel layer.   
     
     
         20 . The structure according to  claim 19 , wherein sidewalls of the first gate dielectric extend beyond sidewalls of the first channel layer, sidewalls of the insulating layer, sidewalls of the second channel layer, sidewalls of the second gate dielectric and sidewalls of the second gate structure.