Circuits and Methods for a Noise Shaping Analog To Digital Converter

Abstract

Systems and methods are provided for analog-to-digital conversion (ADC). A first quantization stage may be configured to receive an analog input signal and sample the analog input signal to generate a first digital signal, the first quantization stage may be further configured to filter the first digital signal with a first noise-shaping transfer function to generate a first noise-shaped digital output and to generate a quantization error signal based on a comparison of the analog input signal and the first noise-shaped digital output. A voltage controlled oscillator (VCO)-based second quantization stage may be configured to receive the quantization error signal and sample the quantization error signal to generate a second digital signal, the VCO-based second quantization stage may be further configured to filter the second digital signal with a second noise-shaping transfer function to generate a second noise-shaped digital output. A first digital filter may be configured to filter the first noise-shaped digital output with an equivalent signal transfer function of the VCO-based second quantization stage to generate a first stage digital output. A second digital filter may be configured to filter the second noise-shaped digital output with the first noise-shaping transfer function to generate a second stage digital output with second order noise-shaping characteristics A combination circuit may combine the first stage digital output and the second stage digital output to generate a digital ADC output signal with second order noise shaping characteristics.

1 . A circuit comprising:
 a first quantization stage configured to receive a quantization error signal, to sample the quantization error signal, to generate a first digital signal, to filter the first digital signal, and to generate a first noise-shaped digital output; and   a first digital filter configured to filter the first noise-shaped digital output and to generate a first stage digital output.   
     
     
         2 . The circuit of  claim 1 , wherein the first quantization stage includes an open loop voltage controlled oscillator (VCO)-based quantizer. 
     
     
         3 . The circuit of  claim 1 , further comprising a second quantization stage configured to receive an analog input signal, to sample the analog input signal, to generate a second digital signal, to filter the second digital signal with a second noise shaping transfer function, to generate a second noise-shaped digital output, and to generate the quantization error signal based on a comparison of the analog input signal and the second noise-shaped digital output, wherein the second quantization stage includes a successive approximation register (SAR) quantizer. 
     
     
         4 . The circuit of  claim 3 , wherein the quantization error signal is determined based on a residue voltage produced by the SAR quantizer during generation of the second noise-shaped digital output. 
     
     
         5 . The circuit of  claim 3 , wherein the second quantization stage is configured to filter the second digital signal using a loop filter with the second noise-shaping transfer function. 
     
     
         6 . The circuit of  claim 3 , further comprising:
 a second digital filter configured to filter the second noise-shaped digital output with an equivalent signal transfer function and to generate a second stage digital output; and   a combination circuit configured to combine the first stage digital output and the second stage digital output and to generate a digital analog-to-digital conversion (ADC) output signal with a second-order noise-shaping characteristic, wherein the combination circuit is an adder circuit.   
     
     
         7 . The circuit of  claim 3 , wherein the second quantization stage is further configured to delay the quantization error signal by a clock cycle, to generate a delayed quantization error signal, and to subtract the delayed quantization error signal from the analog input signal in a feedback loop. 
     
     
         8 . The circuit of  claim 1 , wherein the first quantization stage is configured to receive an inversion of the quantization error signal. 
     
     
         9 . The circuit of  claim 1 , wherein the first quantization stage is configured to filter the first digital signal with a first noise-shaping transfer function that approximates a first-order difference operation. 
     
     
         10 . A circuit comprising:
 a first quantization stage configured to generate a quantization error signal; and   a second quantization stage configured to receive the quantization error signal, to sample the quantization error signal, to generate a second digital signal, to filter the second digital signal, and to generate a second noise-shaped digital output.   
     
     
         11 . The circuit of  claim 10 , wherein:
 the first quantization stage is further configured to receive an analog input signal, to sample the analog input signal based on a first input clock signal, to generate a first digital signal, to filter the first digital signal with a first noise-shaping transfer function, to generate a first noise-shaped digital output, and to generate the quantization error signal based on a comparison of the analog input signal and the first noise-shaped digital output; and   the second quantization stage is configured to sample the quantization error signal based on a second input clock signal that has a higher frequency than the first input clock signal and to filter the second digital signal with a second noise-shaping transfer function, the circuit further comprising:   a digital up-sampler configured to increase a sampling rate of the first noise-shaped digital output by an amount proportional to a ratio of the second input clock signal and the first input clock signal and to generate an up-sampled digital output;   a first digital filter configured to filter the up-sampled digital output with an equivalent signal transfer function and to generate a first stage digital output;   a second digital filter configured to filter the second noise-shaped digital output with the first noise-shaping transfer function and to generate a second stage digital output with a second-order noise-shaping characteristic; and   a combination circuit configured to combine the first stage digital output and the second stage digital output and to generate a digital analog-to-digital conversion (ADC) output signal with the second-order noise-shaping characteristic.   
     
     
         12 . The circuit of  claim 10 , wherein the second quantization stage includes an open loop voltage controlled oscillator (VCO)-based quantizer. 
     
     
         13 . The circuit of  claim 10 , wherein the first quantization stage includes a successive approximation register (SAR) quantizer. 
     
     
         14 . The circuit of  claim 10 , wherein the second quantization stage is configured to receive an inversion of the quantization error signal. 
     
     
         15 . A method comprising:
 filtering a first noise-shaped digital output with an equivalent signal transfer function to generate a first stage digital output;   filtering a second noise-shaped digital output with a first noise-shaping transfer function to generate a second stage digital output; and   combining the first stage digital output and the second stage digital output to generate a digital analog-to-digital conversion (ADC) output signal.   
     
     
         16 . The method of  claim 15 , further comprising:
 receiving an analog input signal at a first quantization stage;   sampling the analog input signal at the first quantization stage to generate a first digital signal;   filtering the first digital signal with the first noise-shaping transfer function to generate the first noise-shaped digital output;   generating a quantization error signal at the first quantization stage based on a comparison of the analog input signal and the first noise-shaped digital output;   receiving the quantization error signal at a second quantization stage;   sampling the quantization error signal to generate a second digital signal; and   filtering the second digital signal with a second noise-shaping transfer function to generate the second noise-shaped digital output, wherein the second stage digital output and the digital ADC output signal are generated with a second-order noise-shaping characteristic and the first quantization stage includes a successive approximation register (SAR) quantizer.   
     
     
         17 . The method of  claim 16 , further comprising determining the quantization error signal based on a residue voltage produced by the SAR quantizer during generation of the first noise-shaped digital output. 
     
     
         18 . The method of  claim 16 , wherein the second quantization stage is configured to receive an inversion of the quantization error signal. 
     
     
         19 . The method of  claim 16 , wherein the second noise-shaping transfer function approximates a first-order difference operation. 
     
     
         20 . The method of  claim 16 , further comprising:
 delaying the quantization error signal by a clock cycle to generate a delayed quantization error signal; and   subtracting the delayed quantization error signal from the analog input signal in a feedback loop.