Thin-film transistor and manufacturing method thereof

Abstract

A body layer formed of a semiconductor layer, the body layer comprising, a first region, a second region, and a channel region positioned therebetween; a channel stopper formed on the channel region; source and drain electrodes electrically connected to the first and second regions via first and second contact layers respectively are provided. Each of the first and second contact layers comprises an impurities-containing first amorphous silicon layer; a thickness of each of the first and second regions is less than a thickness of the channel region; and the first and second regions comprise a second amorphous silicon layer containing impurities in a concentration being less than a concentration of impurities contained in the first amorphous silicon layer. This makes it possible to suppress a photoexcited current and improve the aperture ratio in a case that a display apparatus is configured.

What is claimed is: 
     
         1 . A manufacturing method for a thin-film transistor, the manufacturing method comprising:
 forming a gate electrode and a first insulation layer, in this order, on a substrate;   depositing, on the first insulation layer, a first amorphous silicon film, and a second insulation layer in this order, wherein the first amorphous silicon film is non-doped;   forming a channel stopper by patterning the second insulation layer on a first portion of the first amorphous silicon film, wherein the first portion is to be a channel region;   forming a recess in the first amorphous silicon film by etching a second portion of the first amorphous silicon film, wherein the second portion is not covered by the channel stopper, thereby forming, above the gate electrode, a body layer from the first amorphous silicon film, wherein the body layer comprises a first region, a second region, and the channel region being positioned between the first region and the second region, a thickness of the channel region is greater than a thickness of each of the first region and the second region;   depositing a second amorphous silicon film comprising a first amorphous silicon layer above the body layer and the channel stopper, wherein the first amorphous silicon layer is impurities-containing;   depositing a conductor layer on the second amorphous silicon film; and   forming, from the second amorphous silicon film, a first contact layer that is positioned on the first region and a second contact layer that is positioned on the second region, and forming, from the conductor layer, a source electrode that is in direct contact with the first amorphous silicon layer of the first contact layer and that is electrically connected to the first region via the first contact layer and a drain electrode that is in direct contact with the first amorphous silicon layer of the second contact layer and that is electrically connected to the second region via the second contact layer, by patterning the conductor layer and the second amorphous silicon film.   
     
     
         2 . The manufacturing method for the thin-film transistor according to  claim 1 , wherein the channel region of the body layer is formed of non-doped amorphous silicon; and
 each of the first region and the second region of the body layer comprises a second amorphous silicon layer containing impurities in a concentration being less than a concentration of the first amorphous silicon layer.   
     
     
         3 . The manufacturing method for the thin-film transistor according to  claim 1 , wherein a concentration of impurities contained in the first amorphous silicon layer is 1E18 (pieces/cm 3 ) to 1E20 (pieces/cm 3 ). 
     
     
         4 . The manufacturing method for the thin-film transistor according to  claim 1 , wherein the thickness of each of the first region and the second region of the body layer is 30% to 70% of the thickness of the channel region of the body layer. 
     
     
         5 . The manufacturing method for the thin-film transistor according to  claim 2 , wherein a concentration of impurities contained in the second amorphous silicon layer is 1E15 (pieces/cm 3 ) to 1E17 (pieces/cm 3 ). 
     
     
         6 . The manufacturing method for the thin-film transistor according to  claim 2 , wherein a concentration of impurities contained in the first amorphous silicon layer is greater than or equal to 100 times and less than or equal to 10000 times a concentration of impurities contained in the second amorphous silicon layer.