Method of manufacturing a semiconductor device and a semiconductor device

Abstract

In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, the method comprising:
 forming a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure;   forming an interlayer dielectric (ILD) layer over the fin structure;   forming an opening in the ILD layer such that a source/drain region of the fin structure is exposed in the opening;   removing the first semiconductor layers from the source/drain region of the fin structure is exposed in the opening;   forming a third semiconductor layer to fully wrap around each of the first semiconductor layers within the opening;   performing a heating process to make an upper surface of the third semiconductor layer substantially flat; and   forming a conductive contact layer over the first semiconductor layer.   
     
     
         2 . The method of  claim 1 , further comprising, after the heating process is performed and before the conductive contact is formed, forming a fourth semiconductor layer over the third semiconductor layer and an upper surface of the interlayer dielectric layer. 
     
     
         3 . The method of  claim 1 , wherein the third semiconductor layer is Ge or Si 1-x Ge x , where 0.3<x<1. 
     
     
         4 . The method of  claim 3 , wherein the third semiconductor layer is doped with phosphorous. 
     
     
         5 . The method of  claim 3 , wherein:
 the third semiconductor layer is epitaxially formed at a substrate temperature in a range from 350° C. to 410° C., and   the heating process is performed at the substrate temperature in a range from 410° C. to 470° C.   
     
     
         6 . The method of  claim 3 , wherein:
 the fourth semiconductor layer is Si or Si 1-y Ge y , where 0<y<0.3, and   the fourth semiconductor layer is formed at a substrate temperature in a range from 410° C. to 470° C.   
     
     
         7 . The method of  claim 6 , wherein the fourth semiconductor layer is amorphous or polycrystalline. 
     
     
         8 . The method of  claim 6 , wherein the fourth semiconductor layer is doped with phosphorous. 
     
     
         9 . The method of  claim 1 , wherein no void is formed at a bottom or sides of the third semiconductor layer. 
     
     
         10 . The method of  claim 1 , wherein side faces of the third semiconductor layer and side faces of the conductive contact are in contact with an inner wall of the opening. 
     
     
         11 . A method of manufacturing a semiconductor device, the method comprising:
 forming a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure, a source/drain region of the fin structure protruding from an isolation insulating layer;   forming an interlayer dielectric (ILD) layer over the fin structure;   forming an opening in the ILD layer such that a source/drain region of the fin structure is exposed in the opening;   removing the first semiconductor layers from the source/drain region of the fin structure is exposed in the opening;   forming a third semiconductor layer to fully wrap around each of the first semiconductor layers within the opening;   performing a heating process to reflow the third semiconductor layer;   forming a fourth semiconductor layer over the third semiconductor layer; and   forming a conductive contact layer on the fourth semiconductor layer.   
     
     
         12 . The method of  claim 11 , wherein after the heating process is performed, a thickness variation of the third semiconductor layer in the opening is less than or equal to 5 nm. 
     
     
         13 . The method of  claim 12 , wherein after the heating process is performed, the thickness variation of the third semiconductor layer in the opening is more than or equal to 0.2 nm. 
     
     
         14 . The method of  claim 11 , further comprising, after the fourth semiconductor layer is formed and before the conductive contact is formed, annealing the third and fourth semiconductor layers. 
     
     
         15 . The method of  claim 14 , wherein the annealing operation is performed by a laser annealing method. 
     
     
         16 . The method of  claim 11 , wherein the forming the third semiconductor layer, the performing the heating process and the forming the fourth semiconductor layer are performed in a same manufacturing apparatus. 
     
     
         17 . The method of  claim 11 , wherein the heating process and the forming the fourth semiconductor layer are performed at a same substrate temperature. 
     
     
         18 . The method of  claim 11 , wherein a growth rate of the third semiconductor layer is in a range from 5 nm/min to 15 nm/min. 
     
     
         19 . A method of manufacturing a semiconductor device, the method comprising:
 forming a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure, a source/drain region of the fin structure protruding from an isolation insulating layer;   forming an interlayer dielectric (ILD) layer over the fin structure;   forming an opening in the ILD layer such that a source/drain region of the fin structure is exposed in the opening;   removing the first semiconductor layers from the source/drain region of the fin structure is exposed in the opening;   forming a third semiconductor layer to fully wrap around each of the first semiconductor layers within the opening;   performing a heating process to make an upper surface of the third semiconductor layer substantially flat; and   forming a conductive contact layer over the third semiconductor layer.   
     
     
         20 . The method of  claim 19 , wherein the source/drain regions are (i) portions of multiple fins protruding from an isolation insulating layer, or (ii) portions of semiconductor wires horizontally extending over the isolation insulating layer.