Devices with strained isolation features
Abstract
A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method comprising:
forming a first/source drain feature on a first fin disposed on a substrate, wherein the first fin is at least partially embedded within a first isolation layer; removing a portion of the first isolation layer such that the first isolation layer has a concave top surface defining a recess; forming an etch stop layer within the recess on the concave top surface of the first isolation layer; forming a second isolation layer on the etch stop layer within the recess; and performing a treatment process on the second isolation layer to thereby cause the second isolation layer to impart a tensile stress on the first fin.
2 . The method of claim 1 , wherein the forming of the etch stop layer within the recess on the concave top surface of the first isolation layer includes forming the etch stop layer directly on the concave top surface of the first isolation layer.
3 . The method of claim 1 , wherein the forming of the etch stop layer within the recess on the concave top surface of the first isolation layer includes forming the etch stop layer directly on the first source/drain feature.
4 . The method of claim 1 , wherein the forming of the second isolation layer on the etch stop layer within the recess includes forming the first isolation layer directly on the etch stop layer within the recess.
5 . The method of claim 4 , wherein the forming of the second isolation layer on the etch stop layer within the recess includes forming the first isolation layer over the first source/drain feature such that the second isolation layer covers the first source/drain feature.
6 . The method of claim 1 , wherein the first isolation layer has a different material composition than the second isolation layer.
7 . The method of claim 1 , wherein the first source/drain feature includes an n-type dopant.
8 . The method of claim 1 , wherein the performing of the treatment process on the second isolation layer to thereby cause the second isolation layer to impart a tensile stress on the first fin includes applying an annealing process to the second isolation layer.
9 . A method comprising:
providing a first fin structure and a second fin structure disposed on a substrate, wherein a first isolation layer extends from the first fin structure to the second fin structure; forming a recess within the first isolation layer between the first and second fin structures; forming a second isolation layer within the recess and over the first and second fin structure; and performing a treatment process on the second isolation layer to thereby cause the second isolation layer to impart a tensile stress on the first and second fin structures.
10 . The method of claim 9 , further comprising forming an etch stop layer in the recess directly on the first isolation layer, and
wherein the etch stop layer prevents the second isolation layer from interfacing with the first isolation layer.
11 . The method of claim 9 , further comprising a first source/drain feature on the first fin structure, and
wherein the second isolation layer extends to a greater height above the substrate than the first source/drain feature after the forming of the second isolation layer.
12 . The method of claim 9 , wherein forming a recess within the first isolation layer between the first and second fin structures includes performing a wet etching process.
13 . The method of claim 9 , wherein forming a recess within the first isolation layer between the first and second fin structures includes performing a dry etching process.
14 . The method of claim 9 , further comprising forming a gate structure on the first and second fin structures.
15 . A method comprising:
forming a first fin on a substrate; forming a shallow trench isolation structure on the substrate, wherein the first fin is at least partially embedded within the shallow trench isolation structure; recessing the shallow trench isolation structure such that the recessed shallow trench isolation structure has a concave top surface defining a recess; forming an isolation layer within the recess; and performing a treatment process on the isolation layer to thereby cause the isolation layer to impart a tensile stress on the first fin.
16 . The method of claim 15 , wherein the performing of the treatment process includes annealing the isolation layer at a temperature ranging from about 500° C. to about 1200° C.
17 . The method of claim 15 , wherein the performing of the treatment process includes applying an annealing process to the isolation layer, and
wherein the annealing process is selected from the group consisting of a furnace annealing process, a rapid thermal annealing process, a spike annealing process and a laser annealing process.
18 . The method of claim 15 , further comprising forming a source/drain feature on the first fin prior to the performing of the treatment process on the isolation layer.
19 . The method of claim 15 , wherein the recessing of the shallow trench isolation structure includes anisotropically etching the shallow trench isolation structure.
20 . The method of claim 15 , further comprising forming a gate structure over the first fin, the gate structure includes a gate dielectric layer and a gate electrode layer.Join the waitlist — get patent alerts
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