Structure for reducing source/drain contact resistance at wafer backside

Abstract

A semiconductor structure includes a power rail; an isolation structure over the power rail; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature; one or more channel layers over the isolation structure and connecting the first and the second S/D features; a first via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail; and a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the power rail. The first via structure has a first width in a first cross-section perpendicular to the first direction, the first dielectric feature has a second width in a second cross-section parallel to the first cross-section, and the first width is greater than the second width.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a power rail;   an isolation structure over the power rail;   first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature;   one or more channel layers over the isolation structure and connecting the first and the second S/D features;   a first via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail; and   a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the power rail, wherein the first via structure has a first width in a first cross-section perpendicular to the first direction, the first dielectric feature has a second width in a second cross-section parallel to the first cross-section, and the first width is greater than the second width.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the first width is greater than the second width by about 10% to about 40%. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the first width is greater than the second width by about 4 nm to about 20 nm. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein an outermost layer of the first dielectric feature is a portion of a silicon nitride liner, and the via structure adjoins the isolation structure in the first cross-section and adjoins the silicon nitride liner in a third cross-section along the first direction. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the first cross-section is through each of the first and second source/drain features. 
     
     
         6 . The semiconductor structure of  claim 5 , wherein the second cross-section is through each of the first and second source/drain features. 
     
     
         7 . The semiconductor structure of  claim 1 , further comprising:
 a silicide feature disposed between the first via structure and the first S/D feature.   
     
     
         8 . The semiconductor structure of  claim 7 , further comprising:
 a gap disposed adjacent the silicide feature, wherein the gap extends from the first via structure to the first S/D feature.   
     
     
         9 . The semiconductor structure of  claim 1 , wherein the first via structure directly interfaces the isolation structure. 
     
     
         10 . A semiconductor structure, comprising:
 a backside power rail;   an isolation structure having a first surface interfacing the backside power rail;   first and second source/drain (S/D) features over a second surface of the isolation structure, the second surface opposing the first surface;   a plurality of channel layers over the isolation structure and connecting the first and the second S/D features;   a first via structure extending through the isolation structure and electrically connecting the first S/D feature and the backside power rail; and   a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the backside power rail, wherein along a first cross-sectional view the first via structure has a first width and the first dielectric feature has a second width, and the first width is greater than the second width.   
     
     
         11 . The semiconductor structure of  claim 10 , wherein the first via structure comprises a first conductive material, and wherein the first width is measured from a first sidewall of the first conductive material to a second sidewall of the first conductive material, wherein the second sidewall is opposing the first sidewall. 
     
     
         12 . The semiconductor structure of  claim 11 , wherein the first conductive material is tungsten. 
     
     
         13 . The semiconductor structure of  claim 10 , wherein the isolation structure comprises a first dielectric material and a second dielectric material on the first dielectric material, and wherein the second width is measured from a first sidewall of the first dielectric material to a second sidewall of the first dielectric material, wherein the second sidewall is opposing the first sidewall. 
     
     
         14 . The semiconductor structure of  claim 10 , wherein the isolation structure comprises a liner layer defining bounds of the isolation structure, and wherein the second width is measured between an edge of the liner layer on a first side of the isolation structure to an edge of the liner layer on a second side of the isolation structure. 
     
     
         15 . The semiconductor structure of  claim 10 , wherein the first width is greater than the second width by about 10% to about 40%. 
     
     
         16 . The semiconductor structure of  claim 10 , further comprising:
 a silicide feature formed on the first source/drain feature, the first via structure interfacing the silicide feature; and   an air gap disposed between the silicide feature and the first isolation structure.   
     
     
         17 . A semiconductor structure, comprising:
 a power rail;   an isolation structure comprising a first insulating material having a first surface interfacing the power rail;   first and second source/drain (S/D) features over a second surface of the isolation structure, the second surface opposing the first surface;   a dielectric fin extending between the first S/D feature and the second S/D feature in a first cross-sectional view;   a plurality of channel layers over the isolation structure and connecting the first and the second S/D features in a second cross-sectional view;   a first via structure extending through the isolation structure and electrically connecting the first S/D feature and the power rail;   a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the power rail;   an air gap between the second source/drain feature and a first sidewall of the dielectric fin;   wherein the first via structure interfaces a second sidewall of the dielectric fin.   
     
     
         18 . The semiconductor structure of  claim 17 , further comprising:
 a silicide feature disposed between the first S/D feature and the first via structure.   
     
     
         19 . The semiconductor structure of  claim 18 , wherein the silicide feature interfaces the dielectric fin. 
     
     
         20 . The semiconductor structure of  claim 17 , wherein the first via structure has a first width greater than a second width of the first dielectric feature, the first width and the second width measured in the first cross-sectional view.