Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same

Abstract

The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

1 . A semiconductor structure, comprising:
 a substrate;   a plurality of nano structures vertically stacked over the substrate, the plurality of nano structures comprises an upper nano structure and one or more lower nano structures between the upper nano structure and the substrate;   a semiconductor region adjacent to and laterally contacting each of the one or more lower nano structures;   a gate structure over the plurality of nano structures; and   a first dielectric structure laterally between the semiconductor region and the gate structure, the first dielectric structure being between the upper nano structure and the semiconductor region, the first dielectric structure having a hat-shaped profile between the semiconductor region and the gate structure.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the hat-shaped profile includes a dome-shaped portion and a brim-shaped portion. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the first dielectric structure extends between the upper nano structure and the semiconductor region. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the hat-shaped profile has an apex pointing to the gate structure. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein each of the lower nano structures has a first segment and a second segment, the first segment having a diameter smaller than a diameter of the second segment. 
     
     
         6 . The semiconductor structure of  claim 5 , wherein the first segment is between the second segment and the semiconductor region. 
     
     
         7 . The semiconductor structure of  claim 1 , further comprising a gate spacer over and contacting the first dielectric structure and adjacent to the gate structure, the gate spacer including a dielectric material different than that of the first dielectric structure. 
     
     
         8 . The semiconductor structure of  claim 7 , wherein the dielectric material of the first dielectric structure has a dielectric constant higher than the dielectric material of the gate spacer. 
     
     
         9 . The semiconductor structure of  claim 7 , wherein the first dielectric structure extends along sidewalls of the gate spacer. 
     
     
         10 . A semiconductor device comprising:
 a substrate;   a plurality of nano structures over the substrate, the plurality of nano structures comprising an upper nano structure and lower nano structures between the upper nano structure and the substrate;   a gate structure over the plurality of nano structures, the gate structure comprising a gate dielectric and a gate electrode, the gate structure being between adjacent ones of the lower nano structures and between the upper nano structure and an upper one of the lower nano structures;   an outer spacer laterally adjacent the gate structure;   an inner spacer structure adjacent the gate structure, the inner spacer structure having portions being between adjacent ones of the lower nano structures, the inner spacer structure extending below the outer spacers; and   a first source/drain region contacting an end of the lower nano structures, wherein the inner spacer structure extends between the upper nano structure and the first source/drain region.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the inner spacer structure extends along a vertical sidewall of the outer spacer. 
     
     
         12 . The semiconductor device of  claim 10 , wherein the inner spacer structure has a hat-shaped profile between the gate structure and the first source/drain region. 
     
     
         13 . The semiconductor device of  claim 12 , wherein a crown of the hat-shaped profile faces toward the gate structure. 
     
     
         14 . The semiconductor device of  claim 10 , wherein the gate electrode has a concave surface facing the first source/drain region. 
     
     
         15 . The semiconductor device of  claim 10 , wherein each of lower nano structures comprises a first segment and a second segment with the second segment having a larger diameter than the first segment, and the first source/drain region laterally contacts an edge portion of first segment, wherein the first segment is between the first source/drain region and the second segment. 
     
     
         16 . A semiconductor device comprising:
 a substrate;   a channel region including a plurality of nano structures over the substrate, the plurality of nano structures comprising one or more lower nano structures and an upper nano structure over the one or more lower nano structures;   a gate structure over the channel region, the gate structure comprising a gate dielectric and a gate electrode, the gate structure being interposed between adjacent ones of the plurality of nano structures;   an outer spacer laterally adjacent the gate structure;   an inner spacer structure adjacent the gate structure, the inner spacer structure comprising a plurality of inner spacers, each of the inner spacers being interposed between adjacent ones of the one or more lower nano structures, the inner spacer structure extending below the channel region; and   a first source/drain region adjacent the channel region, the inner spacer structure extending between the upper nano structure and the first source/drain region.   
     
     
         17 . The semiconductor device of  claim 16 , wherein the one or more lower nano structures extend past a lateral boundary of the outer spacer toward the first source/drain region. 
     
     
         18 . The semiconductor device of  claim 16 , further comprising a second source/drain region adjacent the channel region, wherein the channel region is between the first source/drain region and the second source/drain region, wherein each of the one or more lower nano structures comprises:
 a first segment at an edge closest to the first source/drain region, the first segment having a first thickness;   a second segment adjacent to the first segment, the second segment having a second thickness greater than the first thickness; and   a third segment at an edge closest to the second source/drain region, the second segment being between the first segment and the third segment, the third segment having a third thickness less than the second thickness.   
     
     
         19 . The semiconductor device of  claim 16 , wherein each inner spacer of the plurality of inner spacers have a hat-shaped profile. 
     
     
         20 . The semiconductor device of  claim 16 , wherein the inner spacer structure extends along a sidewall of the outer spacer.