Integration of low and high voltage devices on substrate

Abstract

The present disclosure relates to a semiconductor structure that includes a well region and a semiconductor substrate. The well region is disposed within the semiconductor substrate. The well region includes a plurality of first regions separated by a plurality of second regions, where the plurality of first regions is of a first doping and the plurality of second regions are of a second doping different than the first doping. A gate electrode overlies the well region where the gate electrode is disposed laterally over a portion of the plurality of first regions and a portion of the plurality of second regions.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a well region disposed within a semiconductor substrate;   the well region comprising a plurality of first regions separated by a plurality of second regions, wherein the plurality of first regions are of a first doping and the plurality of second regions are of a second doping different than the first doping; and   a gate electrode overlying the well region wherein the gate electrode is disposed laterally over a portion of the plurality of first regions and a portion of the plurality of second regions.   
     
     
         2 . The semiconductor structure of  claim 1 , further comprising a source wherein the source is disposed laterally over a subset of the plurality of first regions and a subset of the plurality of second regions. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein a top surface of the source is level with a first top surface of the plurality of first regions and wherein a bottom surface of the source is above a second top surface of the plurality of first regions. 
     
     
         4 . The semiconductor structure of  claim 2 , wherein a top surface of the plurality of first regions or a top surface of the plurality of second regions are curved. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein a width of the plurality of first regions is different than a width of the plurality of second regions. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the plurality of first regions extends in a lateral direction perpendicular to a longest length of the gate electrode. 
     
     
         7 . The semiconductor structure of  claim 6 , further comprising a gate dielectric between the gate electrode and the well region, wherein the gate dielectric is disposed within an interlayer dielectric (ILD) layer that overlies the semiconductor substrate. 
     
     
         8 . The semiconductor structure of  claim 7 , further comprising a shallow trench isolation (STI) structure disposed within the semiconductor substrate, wherein the STI structure laterally surrounds the plurality of first regions and the plurality of second regions. 
     
     
         9 . A semiconductor structure comprising:
 a well region disposed within a semiconductor substrate;   the well region comprising a plurality of first regions separated by a plurality of second regions; and   a gate electrode overlying the well region wherein the plurality of first regions and plurality of second regions extend vertically beneath the gate electrode from a top surface of the well region to a bottom surface of the well region.   
     
     
         10 . The semiconductor structure of  claim 9 , wherein the plurality of first regions are of a first doping concentration and the plurality of second regions are of a second doping concentration different than the first doping concentration. 
     
     
         11 . The semiconductor structure of  claim 9 , wherein the plurality of second regions extends laterally past an outer edge of the gate electrode. 
     
     
         12 . The semiconductor structure of  claim 9 , further comprising a source or a drain laterally offset from the gate electrode wherein the plurality of first regions or the plurality of second regions extend from a bottom surface of the source or the drain to a bottom surface of the well region; and
 the plurality of first regions or the plurality of second regions extend laterally past an outer edge of the source or the drain.   
     
     
         13 . The semiconductor structure of  claim 9 , further comprising a first top surface of the plurality of first regions aligned beneath the gate electrode and a second top surface of the plurality of first regions laterally offset from the gate electrode wherein the second top surface of the plurality of first regions is below the first top surface of the plurality of first regions. 
     
     
         14 . The semiconductor structure of  claim 13 , further comprising a conductive contact aligned over the second top surface. 
     
     
         15 . The semiconductor structure of  claim 14 , wherein the conductive contact is separated from the second top surface by a source or a drain. 
     
     
         16 . The semiconductor structure of  claim 9 , wherein outermost edges of the plurality of first regions laterally extends from outside of an outer edge of the gate electrode to a region within the outer edge of the gate electrode. 
     
     
         17 . A semiconductor device comprising:
 a gate electrode overlying a semiconductor substrate;   a source and a drain disposed within the semiconductor substrate extending away from outer edges of the gate electrode; and   a plurality of first regions separated by a plurality of second regions that extend from under the gate electrode, source, and drain, wherein a doping of the source and the drain is different than a doping of the plurality of first regions and the plurality of second regions, and a doping of the plurality of first regions is different than a doping of the plurality of second regions.   
     
     
         18 . The semiconductor device of  claim 17 , further comprising a shallow trench isolation (STI) structure disposed within the semiconductor substrate, wherein the plurality of first regions or the plurality of second regions separates the STI structure from the source and the drain. 
     
     
         19 . The semiconductor device of  claim 18 , wherein at a bottom surface of the STI structure, the semiconductor substrate separates the STI structure from the plurality of first regions and the plurality of second regions. 
     
     
         20 . The semiconductor device of  claim 17 , wherein the plurality of first regions and the plurality of second regions laterally surround the gate electrode, the source, and the drain.