Profile Control Of Gate Structures In Semiconductor Devices

Abstract

An integrated circuit (IC) with active and dummy device cell arrays and a method of fabricating the same are discloses. The IC includes a substrate, an active device cell, and a dummy device cell. The active device cell includes an array of source/drain (S/D) regions of a first conductivity type disposed on or within the substrate and an array of gate structures with a first gate fill material disposed on the substrate. The dummy device cell includes a first array of S/D regions of the first conductivity type disposed on or within the substrate, a second array of S/D regions of a second conductivity type disposed on or within the substrate, and an array of dual gate structures disposed on the substrate. Each of the dual gate structures includes the first gate fill material and a second gate fill material that is different from the first gate fill material.

What is claimed is: 
     
         1 . A method, comprising:
 forming first and second fin structures on a substrate;   forming first and second source/drain (S/D) regions on the first and second fin structures, respectively;   forming first and second polysilicon structures on the first and second fin structures, respectively;   replacing the first polysilicon structure and a first portion of the second polysilicon structure with a first metal layer;   polishing the first metal layer at a first polishing rate;   replacing a second portion of the second polysilicon structure with a second metal layer that is different from the first metal layer; and   polishing the second metal layer at a second polishing rate that is different from the first polishing rate.   
     
     
         2 . The method of  claim 1 , wherein replacing the first polysilicon structure and the first portion of the second polysilicon structure comprises forming a masking layer on a top surface of the second portion of the second polysilicon structure. 
     
     
         3 . The method of  claim 1 , wherein replacing the first polysilicon structure and the first portion of the second polysilicon structure comprises depositing a dielectric layer on the first and second fin structures and along a sidewall of the second portion of the second polysilicon structure. 
     
     
         4 . The method of  claim 3 , wherein replacing the first polysilicon structure and the first portion of the second polysilicon structure further comprises depositing the first metal layer on the dielectric layer. 
     
     
         5 . The method of  claim 1 , wherein forming the first and second fin structures comprises forming the first and second fin structures substantially parallel to each other. 
     
     
         6 . The method of  claim 1 , wherein forming the first and second polysilicon structures comprises forming the first and second polysilicon structures substantially parallel to each other. 
     
     
         7 . The method of  claim 1 , further comprising forming a third fin structure on the substrate and substantially parallel to the first and second fin structures, wherein the second portion of the second polysilicon structure is formed on the third fin structure. 
     
     
         8 . The method of  claim 1 , wherein replacing the second portion of the second polysilicon structure comprises depositing a dielectric layer along a sidewall of the first metal layer. 
     
     
         9 . The method of  claim 8 , wherein replacing the second portion of the second polysilicon structure further comprises depositing the second metal layer on the dielectric layer. 
     
     
         10 . The method of  claim 1 , wherein replacing the first polysilicon structure and the first portion of the second polysilicon structure comprises performing an oxidation process on the first and second fin structures. 
     
     
         11 . A method, comprising:
 forming first, second, and third fin structures on a substrate;   forming a first polysilicon structure on the first fin structure;   forming a second polysilicon structure comprising a first polysilicon portion on the second fin structure and a second polysilicon portion on the third fin structure;   replacing the first polysilicon structure with a first gate structure;   replacing, at a same time as replacing the first polysilicon structure, the first polysilicon portion with a second gate structure; and   replacing the second polysilicon portion with a third gate structure after replacing the first polysilicon portion.   
     
     
         12 . The method of  claim 11 , wherein forming the first, second, and third fin structures comprises forming the first, second, and third fin structures substantially parallel to each other. 
     
     
         13 . The method of  claim 11 , wherein forming the first and second polysilicon structures comprises forming the first and second polysilicon structures substantially parallel to each other. 
     
     
         14 . The method of  claim 11 , wherein replacing the first polysilicon portion comprises depositing a gate dielectric layer of the second gate structure on the second fin structure and along a sidewall of the second polysilicon portion. 
     
     
         15 . The method of  claim 11 , wherein replacing the second polysilicon portion comprises depositing a gate dielectric layer of the third gate structure on the third fin structure and along a sidewall of the second gate structure. 
     
     
         16 . The method of  claim 11 , wherein replacing the first polysilicon portion comprises forming a masking layer on the second polysilicon portion. 
     
     
         17 . A method, comprising:
 forming first and second n-type source/drain (S/D) regions in a substrate;   forming first and second p-type S/D regions disposed in the substrate;   forming a polysilicon structure comprising a first polysilicon portion between the first and second n-type S/D regions and a second polysilicon portion between the first and second p-type S/D regions;   replacing the first polysilicon portion with a first gate structure; and   replacing the second polysilicon portion with a second gate structure in contact with a sidewall of the first gate structure.   
     
     
         18 . The method of  claim 17 , wherein replacing the first polysilicon portion comprises forming a masking layer on the second polysilicon portion. 
     
     
         19 . The method of  claim 17 , wherein replacing the first polysilicon portion comprises depositing a gate dielectric layer of the first gate structure along a sidewall of the second polysilicon portion. 
     
     
         20 . The method of  claim 17 , wherein replacing the second polysilicon portion comprises depositing a gate dielectric layer of the second gate structure along a sidewall of the first gate structure.