Diagonal via structure

Abstract

An integrated circuit (IC) structure includes a plurality of first metal segments in a first metal layer of a semiconductor substrate, the plurality of first metal segments corresponding to first tracks, a plurality of second metal segments in a second metal layer of the semiconductor substrate adjacent to the first metal layer, the plurality of second metal segments corresponding to second tracks perpendicular to the first tracks, and a plurality of via structures configured to electrically connect the plurality of first metal segments to the plurality of second metal segments. Locations of intersections of the first and second tracks define a grid including a first plurality of diagonal grid lines alternating with a second plurality of diagonal grid lines, the first plurality of diagonal grid lines includes at least three via structures of the plurality of via structures positioned at contiguous intersection locations, and the second plurality of diagonal grid lines is free from including a via structure of the plurality of via structures.

What is claimed is: 
     
         1 . An integrated circuit (IC) structure comprising:
 a plurality of first metal segments in a first metal layer of a semiconductor substrate, the plurality of first metal segments corresponding to first tracks;   a plurality of second metal segments in a second metal layer of the semiconductor substrate adjacent to the first metal layer, the plurality of second metal segments corresponding to second tracks perpendicular to the first tracks; and   a plurality of via structures configured to electrically connect the plurality of first metal segments to the plurality of second metal segments,   wherein   locations of intersections of the first and second tracks define a grid comprising a first plurality of diagonal grid lines alternating with a second plurality of diagonal grid lines,   the first plurality of diagonal grid lines comprises at least three via structures of the plurality of via structures positioned at contiguous intersection locations, and   the second plurality of diagonal grid lines is free from including a via structure of the plurality of via structures.   
     
     
         2 . The IC structure of  claim 1 , wherein
 the first tracks have a first pitch,   the second tracks have a second pitch, and   a ratio of the first pitch to the second pitch is less than √{square root over (3)}.   
     
     
         3 . The IC structure of  claim 2 , wherein the first pitch is greater than the second pitch. 
     
     
         4 . The IC structure of  claim 3 , wherein the plurality of first metal segments overlies the plurality of second metal segments. 
     
     
         5 . The IC structure of  claim 1 , wherein the contiguous intersection locations are adjacent locations along a single grid line of the first plurality of diagonal grid lines. 
     
     
         6 . The IC structure of  claim 1 , wherein the intersection locations have a spacing value ranging from 20 nanometers (nm) to 50 nm. 
     
     
         7 . The IC structure of  claim 1 , wherein the at least three via structures of the plurality of via structures comprise:
 first and second via structures positioned at the contiguous intersection locations being adjacent locations along a first grid line of the first plurality of diagonal grid lines; and   a third via structure positioned at the contiguous intersection location being a location on a second grid line of the first plurality of diagonal grid lines adjacent to the first grid line.   
     
     
         8 . The IC structure of  claim 1 , wherein
 each of the first plurality of diagonal grid lines and the second plurality of diagonal grid lines has a positive slope with respect to one of the first or second tracks,   the grid comprises a third plurality of diagonal grid lines intersecting with the first plurality of diagonal grid lines and having a negative slope with respect to the one of the first or second tracks, and   each contiguous intersection location is separated from at least one other contiguous intersection location by a same distance along one or both of a grid line of the first plurality of diagonal grid lines or a grid line of the third plurality of diagonal grid lines.   
     
     
         9 . An integrated circuit (IC) structure comprising:
 a plurality of first metal segments in a first metal layer of a semiconductor substrate, the plurality of first metal segments corresponding to first tracks;   a plurality of second metal segments in a second metal layer of the semiconductor substrate adjacent to the first metal layer, the plurality of second metal segments corresponding to second tracks perpendicular to the first tracks; and   a plurality of via structures configured to electrically connect the plurality of first metal segments to the plurality of second metal segments,   wherein   locations of intersections of the first and second tracks define a grid comprising a first plurality of diagonal grid lines alternating with a second plurality of diagonal grid lines, and   the first plurality of diagonal grid lines comprises:
 an entirety of the intersection locations at which the via structures of the plurality of via structures are positioned; and 
 at least three via structures of the plurality of via structures positioned at contiguous intersection locations. 
   
     
     
         10 . The IC structure of  claim 9 , wherein
 the first tracks have a first pitch,   the second tracks have a second pitch,   the first pitch is greater than the second pitch, and   a ratio of the first pitch to the second pitch is less than √{square root over (3)}.   
     
     
         11 . The IC structure of  claim 10 , wherein the first metal layer overlies the second metal layer. 
     
     
         12 . The IC structure of  claim 9 , wherein the contiguous intersection locations are adjacent locations along a single grid line of the first plurality of diagonal grid lines or among locations of adjacent grid lines of the first plurality of diagonal grid lines. 
     
     
         13 . The IC structure of  claim 9 , wherein
 each of the first plurality of diagonal grid lines and the second plurality of diagonal grid lines has a positive slope with respect to one of the first or second tracks,   the grid comprises a third plurality of diagonal grid lines intersecting with the first plurality of diagonal grid lines and having a negative slope with respect to the one of the first or second tracks, and   each intersection location at which a via structure of the plurality of via structures is positioned is separated from another intersection location at which another via structure of the plurality of via structures is positioned along one of a grid line of the first plurality of diagonal grid lines or a grid line of the third plurality of diagonal grid lines by a distance equal to a multiple of a via pitch.   
     
     
         14 . The IC structure of  claim 13 , wherein the via pitch has a value ranging from 20 nanometers (nm) to 50 nm. 
     
     
         15 . An integrated circuit (IC) structure comprising:
 a plurality of first metal segments in a first metal layer of a semiconductor substrate, the plurality of first metal segments corresponding to first tracks having a first pitch;   a plurality of second metal segments in a second metal layer of the semiconductor substrate adjacent to the first metal layer, the plurality of second metal segments corresponding to second tracks perpendicular to the first tracks and having a second pitch; and   a plurality of via structures configured to electrically connect the plurality of first metal segments to the plurality of second metal segments,   wherein   a ratio of the first pitch to the second pitch is less than √{square root over (3)},   locations of intersections of the first and second tracks define a grid comprising a first plurality of diagonal grid lines alternating with a second plurality of diagonal grid lines, and   the first plurality of diagonal grid lines comprises:
 an entirety of the intersection locations at which the via structures of the plurality of via structures are positioned; and 
 at least three via structures of the plurality of via structures positioned at contiguous intersection locations. 
   
     
     
         16 . The IC structure of  claim 15 , wherein the plurality of first metal segments in the first metal layer overlies the plurality of second metal segments in the second metal layer. 
     
     
         17 . The IC structure of  claim 16 , wherein the ratio of the first pitch to the second pitch is greater than one. 
     
     
         18 . The IC structure of  claim 15 , wherein
 each of the first plurality of diagonal grid lines and the second plurality of diagonal grid lines has a positive slope with respect to one of the first or second tracks,   the grid comprises a third plurality of diagonal grid lines intersecting with the first plurality of diagonal grid lines and having a negative slope with respect to the one of the first or second tracks, and   intersection locations at which via structures of the plurality of via structures are separated from each other along one of a grid line of the first plurality of diagonal grid lines or a grid line of the third plurality of diagonal grid lines by a distance equal to a multiple of a via pitch.   
     
     
         19 . The IC structure of  claim 18 , wherein the via pitch has a value ranging from 20 nanometers (nm) to 50 nm. 
     
     
         20 . The IC structure of  claim 18 , wherein the contiguous intersection locations are adjacent locations along one or more grid lines of the first plurality of diagonal grid lines and/or the third plurality of diagonal grid lines.