Semiconductor devices and methods of manufacturing thereof

Abstract

A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate that both extend along a first direction. The method includes forming a dielectric fin extending along the first direction and is disposed between the first and second semiconductor fins. The method includes forming a dummy gate structure extending along a second direction and straddling the first and second semiconductor fins and the dielectric fin. The method includes removing a portion of the dummy gate structure over the dielectric fin to form a trench by performing an etching process that includes a plurality of stages. Each of the plurality of stages includes a combination of anisotropic etching and isotropic etching such that a variation of a distance between respective inner sidewalls of the trench along the second direction is within a threshold.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first semiconductor fin and a second semiconductor fin over a first area of a substrate;   a third semiconductor fin and a fourth semiconductor fin over a second area of the substrate;   wherein a first gate isolation structure filled with a dielectric material is formed between the first semiconductor fin and the second semiconductor fin, and a second gate isolation structure filled with the dielectric material is formed between the third semiconductor fin and the fourth semiconductor fin;   wherein a first distance between the first semiconductor fin and the second semiconductor fin is greater than a second distance between the third semiconductor fin and the fourth semiconductor fin; and   wherein a first variation of a first distance between respective inner sidewalls of the first gate isolation structure and a second variation of a second distance between respective inner sidewalls of the second gate isolation structure are each within a threshold.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the threshold is less than about 20%. 
     
     
         3 . The semiconductor device of  claim 1 , wherein a width of the first gate isolation structure is greater than a width of the second gate isolation structure. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the first semiconductor fin, the second semiconductor fin, the third semiconductor fin, and the fourth semiconductor fin each include a gate dielectric layer. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the gate isolation structure comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or silicon oxycarbide. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the first semiconductor fin, the second semiconductor fin, the third semiconductor fin, and the fourth semiconductor fin each comprise at least one of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the first semiconductor fin, the second semiconductor fin, the third semiconductor fin, and the fourth semiconductor fin each comprise at least one of TiN, TaN, Ru, Mo, Al, WN, ZrSi 2 , MoSi 2 , TaSi 2 , NiSi 2 , or WN. 
     
     
         8 . A semiconductor device, comprising:
 a first semiconductor fin and a second semiconductor fin over a first area of a substrate; and   a third semiconductor fin and a fourth semiconductor fin over a second area of the substrate, wherein a first density of transistors formed in the first area is greater than a second density of transistors formed in the second area;   wherein a first gate isolation structure filled with a dielectric material is formed between the first semiconductor fin and the second semiconductor fin, and a second gate isolation structure filled with the dielectric material is formed between the third semiconductor fin and the fourth semiconductor fin; and   wherein a first variation of a first distance between respective inner sidewalls of the first gate isolation structure and a second variation of a second distance between respective inner sidewalls of the second gate isolation structure are each within a threshold.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the threshold is less than about 20%. 
     
     
         10 . The semiconductor device of  claim 8 , wherein the second distance is greater than the first distance. 
     
     
         11 . The semiconductor device of  claim 8 , wherein the gate isolation structure comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or silicon oxycarbide. 
     
     
         12 . The semiconductor device of  claim 8 , wherein a width of the first gate isolation structure is greater than a width of the second gate isolation structure. 
     
     
         13 . A semiconductor device, comprising:
 a first plurality of transistors; and   a second plurality of transistors, the first plurality of transistors configured to operate under a lower gate voltage than the second plurality of transistors;   wherein the first plurality of transistors comprise a first transistor having a first active gate structure and a second transistor having a second active gate structure, the first and second active gate structures being separated from each other by a first gate isolation structure along a first direction;   wherein the second plurality of transistors comprise a third transistor having a third active gate structure and a fourth transistor having a fourth active gate structure, the third and fourth active gate structures being separated from each other by a second gate isolation structure along the first direction; and   wherein a first variation of a first distance between respective sidewalls of the first gate isolation structure along the first direction is about equal to a second variation of a second distance between respective sidewalls of the second gate isolation structure along the first direction, wherein the first and second variations each range from about −20% to about 20%.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each comprise at least one of TiN, TaN, Ru, Mo, Al, WN, ZrSi 2 , MoSi 2 , TaSi 2 , NiSi 2 , or WN. 
     
     
         15 . The semiconductor device of  claim 13 , wherein the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each comprise at least one of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr. 
     
     
         16 . The semiconductor device of  claim 13 , wherein the gate isolation structure comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or silicon oxycarbide. 
     
     
         17 . The semiconductor device of  claim 13 , wherein the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each include a gate dielectric layer. 
     
     
         18 . The semiconductor device of  claim 13 , wherein the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each include a metal gate layer. 
     
     
         19 . The semiconductor device of  claim 13 , wherein a width of the first gate isolation structure is greater than a width of the second gate isolation structure. 
     
     
         20 . The semiconductor device of  claim 13 , wherein a first density of the first plurality of transistors is greater than a second density of the second plurality of transistors.