Etch method for interconnect structure

Abstract

A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first interconnect structure formed of a first metal and having a first horizontal top surface along which germanium is distributed; and   a second interconnect structure formed of a second metal and in contact with the first interconnect structure, the second interconnect structure comprising:
 a first portion disposed above the horizontal top surface of the first interconnect structure; and 
 a second portion disposed below the horizontal top surface and laterally extending beyond sidewalls of the first portion. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first metal is cobalt (Co) and the second metal is tungsten (W). 
     
     
         3 . The semiconductor device of  claim 1 , further comprising a dielectric layer around the first portion of the second interconnect structure. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the dielectric layer comprises silicon nitride (Si 3 N 4 ). 
     
     
         5 . The semiconductor device of  claim 3 , wherein the dielectric layer is disposed above the germanium and the second portion of the second interconnect structure. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the second portion laterally extends to a width of about 9 to 11 nanometers (nm). 
     
     
         7 . The semiconductor device of  claim 1 , wherein the second portion vertically extends to a depth of about 7 to 9 nanometers (nm). 
     
     
         8 . A semiconductor device, comprising:
 a first interconnect structure formed of a first metal;   a second interconnect structure formed of a second metal and comprising:
 a first portion vertically extending into the first interconnect structure; and 
 a second portion disposed above and vertically extending away from the first portion; and 
   a germanium region disposed on top of the first interconnect structure and around the first portion of the second interconnect structure.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the first metal is cobalt (Co) and the second metal is tungsten (W). 
     
     
         10 . The semiconductor device of  claim 8 , further comprising a dielectric layer around the first portion of the second interconnect structure. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the dielectric layer comprises silicon nitride (Si 3 N 4 ). 
     
     
         12 . The semiconductor device of  claim 10 , wherein the dielectric layer is disposed above the germanium and the second portion of the second interconnect structure. 
     
     
         13 . The semiconductor device of  claim 8 , wherein the second portion laterally extends to a width of about 9 to 11 nanometers (nm). 
     
     
         14 . The semiconductor device of  claim 8 , wherein the second portion vertically extends to a depth of about 7 to 9 nanometers (nm). 
     
     
         15 . A semiconductor device, comprising:
 a first interconnect structure formed of a first metal and having a top surface along which germanium is distributed; and   a second interconnect structure formed of a second metal and comprising:
 a first portion vertically extending a first distance and laterally extending a second distance in the first interconnect structure; and 
 a second portion disposed above and vertically extending away from the first portion. 
   
     
     
         16 . The semiconductor device of  claim 15 , further comprising a dielectric layer disposed above a top surface of the first interconnect structure, the dielectric layer comprising Si 3 N 4 . 
     
     
         17 . The semiconductor device of  claim 16 , wherein the dielectric layer is disposed above the top surface comprising the germanium and the second portion of the second interconnect structure. 
     
     
         18 . The semiconductor device of  claim 15 , wherein the first metal is cobalt (Co) and the second metal is tungsten (W). 
     
     
         19 . The semiconductor device of  claim 15 , wherein the second portion laterally extends to a width of about 9 to 11 nanometers (nm). 
     
     
         20 . The semiconductor device of  claim 15 , wherein the second portion vertically extends to a depth of about 7 to 9 nanometers (nm).