Semiconductor structure and forming method thereof

Abstract

A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes receiving a semiconductor substrate having a first region and a second region; forming a dielectric layer over the semiconductor substrate; removing portions of the dielectric layer to form a dielectric structure in the first region, wherein the dielectric structure includes a base structure and a plurality of first isolation structures over the base structure; forming a semiconductor layer covering the first region and the second region; removing a portion of the semiconductor layer to expose a top surface of the plurality of first isolation structures; and forming a plurality of second isolation structures in the second region.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a semiconductor substrate having a first region and a second region;   a first semiconductor layer over the semiconductor substrate and located in the first region;   a dielectric structure over the semiconductor substrate and located in the second region, the dielectric structure having a first upper boundary lower than an upper surface of the first semiconductor layer, wherein the dielectric structure has a first portion extending along a first direction and a second portion extending along a second direction, and the first portion and the second portion are connected to each other;   a second semiconductor layer over the first portion of the dielectric structure;   a first transistor over the first semiconductor layer and located in the first region; and   a second transistor over the second semiconductor layer and located in the second region.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the first transistor is separated from the second transistor by the dielectric structure. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the first direction is substantially a lateral direction, and the second direction is substantially a vertical direction. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the dielectric structure has a second upper boundary substantially level with the upper surface of the first semiconductor layer. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein a first source/drain region of the first transistor interfaces a first sidewall of the second portion of the dielectric structure. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the dielectric structure further includes a third portion extending along the second direction, the third portion connected to the first portion, and the first portion interposing the second portion and the third portion. 
     
     
         7 . The semiconductor structure of  claim 6 , wherein a second source/drain region of the first transistor interfaces a first sidewall of the third portion of the dielectric structure. 
     
     
         8 . A semiconductor structure comprising:
 an isolation feature over a substrate, wherein the isolation feature includes a first portion having a first upper surface and a second portion having a second upper surface, wherein the first upper surface and the second upper surface are substantially planar, and wherein the isolation feature further comprising a third portion, contiguous with the first portion and the second portion, wherein the third portion has a third upper surface, wherein the third upper surface is closer the substrate than the first upper surface; and   a transistor disposed in a semiconductor region above the third upper surface.   
     
     
         9 . The semiconductor structure of  claim 8 , wherein the semiconductor region has a height of 50 nanometers (nm) to about 150 nm and a width of about 5 nm to about 100 nm. 
     
     
         10 . The semiconductor structure of  claim 8 , wherein the isolation feature comprises an oxide. 
     
     
         11 . The semiconductor structure of  claim 8 , further comprising:
 an interlayer dielectric (ILD) on the first upper surface of the isolation feature.   
     
     
         12 . The semiconductor structure of  claim 8 , wherein the isolation feature is deposed in an RF device region of the substrate. 
     
     
         13 . The semiconductor structure of  claim 8 , wherein the transistor is an RF device. 
     
     
         14 . The semiconductor structure of  claim 8 , further comprising:
 another semiconductor region adjacent the second portion of the isolation feature; and   another transistor in the another semiconductor region.   
     
     
         15 . The semiconductor structure of  claim 14 , wherein the another semiconductor region extends to a top of the substrate. 
     
     
         16 . The semiconductor structure of  claim 14 , wherein the another transistor is a logic device and wherein the transistor is an RF device. 
     
     
         17 . A semiconductor structure comprising:
 a semiconductor substrate;   a first semiconductor layer over the semiconductor substrate;   a first isolation feature over the semiconductor substrate, wherein a first sidewall, a bottom surface, and a second sidewall opposing the first sidewall of the first semiconductor layer is defined by the first isolation feature;   a first transistor disposed in the first semiconductor layer above the bottom surface;   a second semiconductor layer over the semiconductor substrate, wherein the second semiconductor layer extends from a surface of the semiconductor substrate; and   a second transistor in the second semiconductor layer.   
     
     
         18 . The semiconductor structure of  claim 17 , wherein the first transistor is an RF transistor and the second transistor is a logic transistor. 
     
     
         19 . The semiconductor structure of  claim 17 , wherein a source/drain region of the first transistor interfaces the first sidewall and another source/drain region of the first transistor interfaces the second sidewall. 
     
     
         20 . The semiconductor structure of  claim 19 , wherein a source/drain region of the second transistor interfaces the first isolation feature.