Method for improved polysilicon etch dimensional control

Abstract

Provided are methods of manufacturing integrated circuit that include a polysilicon etch process in which the wafer having an etch poly pattern is loaded into a reactor chamber and exposed to an activated etchant and, during the etch process, adjusting the temperature conditions within the reactor chamber to increase polymeric deposition on an upper surface of the wafer.

1 . A system for manufacturing an integrated circuit device comprising:
 a reactor chamber configured for etching a wafer;   a gas supply apparatus configured for introducing an etchant gas into the reactor chamber and maintaining a predetermined processing pressure;   a heating apparatus configured for
 heating the reactor chamber to a nominal reactor temperature T n  during a first portion of an etch period, wherein the nominal reactor temperature induces a first polymeric deposition rate DR 1  on an upper surface of the wafer; and 
   heating the reactor chamber to a polymerization temperature T p  during a second portion of the etch period, wherein the polymerization temperature induces a second polymeric deposition rate DR 2  on the upper surface of the wafer and wherein DR 2  is greater than DR 1 .   
     
     
         2 . The system according to  claim 1 , wherein:
 the gas supply apparatus is configured for introducing at least one gas containing at least one halogen atom.   
     
     
         3 . The system according to  claim 1  further comprising:
 the gas supply apparatus configured for introducing at least one gas selected from the group consisting of CF 4 , Cl 2 , and HBr. 
 
     
     
         4 . The system according to  claim 1 , wherein:
 the heating apparatus is further configured for selectively heating a reactor chamber lid assembly when heating the reactor chamber.   
     
     
         5 . heating apparatus configured according to  claim 4 , wherein:
 the heating apparatus is configured for establishing and maintaining a reactor chamber lid polymerization temperature T L  that is at least 3° C. above a reactor chamber lid base operating temperature T b .   
     
     
         6 . The system according to  claim 4 , further comprising:
 the heating apparatus is configured for establishing and maintaining a reactor chamber lid polymerization temperature T L  that is at least 5° C. above a reactor chamber lid base operating temperature T b .   
     
     
         7 . The system according to  claim 1 , further comprising:
 an epitaxial deposition apparatus configured for
 growing a first epitaxial semiconductor material on an exposed surface of the wafer; and 
 growing a second epitaxial semiconductor on an exposed surface of the first epitaxial semiconductor material. 
   
     
     
         8 . The system according to  claim 4 , wherein:
 the heating apparatus comprises a radiant heating assembly within the reactor chamber.   
     
     
         9 . The system according to  claim 7 , wherein:
 the radiant heating assembly is configured for establishing the polymerization temperature T p  within the reactor chamber.   
     
     
         10 . A system for manufacturing an integrated circuit comprising:
 a memory device configured for maintaining an IC design layout;   a processor configured for
 retrieving the IC design layout from the memory device; 
 analyzing the IC design layout for a region in which a poly etch spacing is less than a predetermined target spacing value; and 
 in response to a poly etch spacing that is less than the predetermined target spacing value, modifying a wafer fabrication process to include an enhanced poly etch process; 
   a plasma etch apparatus configured for receiving and etching a series of semiconductor wafers in a reactor chamber;   a gas supply apparatus configured for introducing an etchant gas into the reactor chamber at a predetermined processing pressure;   a power supply apparatus configured for supplying energy to the etchant gas sufficient to convert a portion of the etchant gas within the reactor chamber to a plasma;   a heating apparatus configured for
 heating the reactor chamber to a nominal reactor temperature during a first portion of an etch process and induce a first polymeric deposition rate DR 1  within the reactor chamber; 
 heating the reactor chamber to a polymerization temperature during a second portion of the etch period and induce a second polymeric deposition rate DR 2  on the upper surface of the wafer and wherein DR 2  is greater than DR 1 . 
   
     
     
         11 . The system according to  claim 10 , wherein:
 the gas supply apparatus is further configured for formulating the etchant gas from the group of etchant gases consisting of CF 4 , Cl 2 , HBr, and mixtures thereof.   
     
     
         12 . The system according to  claim 10 , wherein:
 the heating apparatus is further configured for selectively heating a reactor chamber lid to a polymerization temperature T p .   
     
     
         13 . The system according to  claim 12 , wherein:
 the heating apparatus is further configured for selectively heating a reactor chamber lid from a reactor chamber lid base operating temperature T b  to the polymerization temperature T p , wherein the polymerization temperature T p  is at least 5° C. greater than the reactor chamber lid base operating temperature T b .   
     
     
         14 . The system according to  claim 12 , further comprising:
 a temperature measuring apparatus configured for measuring a current temperature of a central region of the reactor chamber lid.   
     
     
         15 . The system according to  claim 10 , wherein:
 the heating apparatus is further configured and operated whereby the second polymeric deposition rate DR 2  is at least 200% of the first polymeric deposition rate DR 1 .   
     
     
         16 . A system for manufacturing an integrated circuit comprising:
 a first deposition apparatus configured for depositing sidewall material adjacent a polysilicon structure on an upper surface of a wafer;   a first etch apparatus configured for etching the sidewall material to form a sidewall adjacent the poly silicon structure;   a first coating apparatus configured for depositing a photosensitive material over the polysilicon structure and the sidewall;   a first patterning apparatus configured for exposing a predetermined portions of the photosensitive material;   a first developing apparatus configured for removing a portion of the photosensitive material to form a poly etch pattern on the photosensitive material and thereby expose a portion of the polysilicon structure;   a first etching apparatus configured for etching the exposed portion of the polysilicon structure, the duration of the etching being sufficient to remove a portion of the exposed polysilicon structure and form an epitaxial recess in the wafer; and   a temperature controlled chamber lid on the first etching apparatus for establishing and maintaining an elevated polymerization temperature within an etch chamber during a portion of the etching and thereby increase a polymer deposition rate.   
     
     
         17 . The system for manufacturing an integrated circuit according to  claim 16 , further comprising:
 a first epitaxial deposition apparatus configured for growing a first epitaxial semiconductor structure from a surface of the epitaxial recess.   
     
     
         18 . The system for manufacturing an integrated circuit according to  claim 16 , wherein:
 the first etching apparatus is configured for utilizing an etchant gas selected from the group consisting of CF 4 , Cl 2 , HBr, and mixtures thereof.   
     
     
         19 . The system for manufacturing an integrated circuit according to  claim 17 , wherein:
 the first epitaxial deposition apparatus further comprises a deposition control apparatus configured for establishing a ratio between a depth of the first epitaxial semiconductor structure and an epitaxial recess height is less than 6.   
     
     
         20 . The system for manufacturing an integrated circuit according to  claim 17 , further comprising:
 a second epitaxial deposition apparatus configured for establishing growing a second epitaxial semiconductor structure from a surface of the first epitaxial semiconductor structure.