Boot process for early display initialization and visualization

Abstract

Embodiments are directed to improving boot process for early display initialization and visualization. An embodiment of a system includes a plurality of processor cores; a cache coupled to the plurality of processor cores; and a controller circuit to: initialize a portion of the cache as static memory for hardware initialization code usage before beginning execution of the hardware initialization code after a power on of the hardware processor; and cause initialization of a display device to be performed using the portion of the cache, the initialization of the display device performed independently of initialization of dynamic memory of the hardware processor.

What is claimed is: 
     
         1 . A hardware processor comprising:
 a plurality of processor cores;   a cache coupled to the plurality of processor cores; and   a controller circuit to:
 responsive to a power on of the hardware processor, initialize a portion of the cache as static memory for hardware initialization code usage before prior to execution of the hardware initialization code; and 
 execute the hardware initialization code using the static memory of the portion of the cache, wherein a boot sequence of the hardware initialization code is distributed across the plurality of processor cores utilizing parallel threads executing on the plurality of processor cores, and wherein the hardware initialization code to cause initialization of a display device to be performed for display device initialization and bring up; 
 wherein initialization and training of dynamic memory of the hardware processor occurs prior to booting to an operation system (OS) and occurs independently of and in parallel with initialization of the display device that utilizes the static memory. 
   
     
     
         2 . The hardware processor of  claim 1 , wherein the hardware initialization code is according to a Basic Input/Output System standard. 
     
     
         3 . The hardware processor of  claim 1 , wherein the hardware initialization code is according to a Unified Extensible Firmware Interface standard. 
     
     
         4 . The hardware processor of  claim 1 , wherein the hardware initialization code executes on the plurality of processor cores in parallel using the portion of the cache as the static memory. 
     
     
         5 . The hardware processor of  claim 1 , wherein the cache is shared by the plurality of processor cores and a graphics core. 
     
     
         6 . The hardware processor of  claim 1 , wherein the cache is an L4 cache. 
     
     
         7 . The hardware processor of  claim 1 , wherein the dynamic memory comprises dynamic random access memory (DRAM). 
     
     
         8 . The hardware processor of  claim 1 , wherein the portion of the cache as the static memory is locked down subsequent to execution of the hardware initialization code to prevent access to the portion. 
     
     
         9 . The hardware processor of  claim 1 , wherein the boot sequence comprises:
 a first boot event of a bootstrap processor (BSP) for handling one or more of a reset vector, processor mode switching, console enabling, creating bootloader memory layout, or chipset initialization;   a second boot event of one of the plurality of processor cores for filling first configuration parameters to initialize the dynamic memory; and   a third boot event of another of the plurality of processor cores for filling second configuration parameter to initialize hardware blocks.   
     
     
         10 . A non-transitory machine-readable medium comprises executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
 responsive to a power on of a hardware processor comprising a plurality of processor cores coupled to a cache, initializing, by a controller, a portion of the cache as static memory for hardware initialization code usage before prior to execution of the hardware initialization code; and   executing the hardware initialization code using the static memory of the portion of the cache, wherein a boot sequence of the hardware initialization code is distributed across the plurality of processor cores utilizing parallel threads executing on the plurality of processor cores, and wherein the hardware initialization code to cause initialization of a display device to be performed for display device initialization and bring up;   performing display device initialization using the static memory from the portion of the cache, the hardware initialization code to cause initialization of a display device to be performed for display device initialization and bring up, wherein initialization and training of the dynamic memory of the system occurs prior to booting to an operation system (OS) and occurs independently of and in parallel with initialization of the display device that utilizes the static memory; and   transferring control of execution of the system from the hardware initialization code to operating system code executing on the system.   
     
     
         11 . The non-transitory machine-readable medium of  claim 10 , wherein the hardware initialization code is according to a Basic Input/Output System standard. 
     
     
         12 . The non-transitory machine-readable medium of  claim 10 , wherein the hardware initialization code is according to a Unified Extensible Firmware Interface standard. 
     
     
         13 . The non-transitory machine-readable medium of  claim 10 , wherein the executing comprises executing the hardware initialization code on the plurality of processor cores in parallel using the portion of the cache as the static memory to initialize the system. 
     
     
         14 . The non-transitory machine-readable medium of  claim 10 , wherein the portion of the cache as the static memory is locked down subsequent to execution of the hardware initialization code to prevent access to the portion. 
     
     
         15 . The non-transitory machine-readable medium of  claim 10 , wherein the boot sequence comprises:
 a first boot event of a bootstrap processor (BSP) for handling one or more of a reset vector, processor mode switching, console enabling, creating bootloader memory layout, or chipset initialization;   a second boot event of one of the plurality of processor cores for filling first configuration parameters to initialize the dynamic memory; and   a third boot event of another of the plurality of processor cores for filling second configuration parameter to initialize hardware blocks.   
     
     
         16 . A system comprising:
 a hardware processor comprising a plurality of processor cores;   a cache coupled to the hardware processor;   storage for hardware initialization code; and   a controller circuit to:
 responsive to a power on of the hardware processor, initialize a portion of the cache as static memory for hardware initialization code usage before prior to execution of the hardware initialization code; and 
 execute the hardware initialization code using the static memory of the portion of the cache, wherein a boot sequence of the hardware initialization code is distributed across the plurality of processor cores utilizing parallel threads executing on the plurality of processor cores, and wherein the hardware initialization code to cause initialization of a display device to be performed for display device initialization and bring up; 
 wherein initialization and training of dynamic memory of the hardware processor occurs prior to booting to an operation system (OS) and occurs independently of and in parallel with initialization of the display device that utilizes the static memory. 
   
     
     
         17 . The system of  claim 16 , wherein the hardware initialization code is according to a Basic Input/Output System standard. 
     
     
         18 . The system of  claim 16 , wherein the hardware initialization code is according to a Unified Extensible Firmware Interface standard. 
     
     
         19 . The system of  claim 16 , wherein the hardware initialization code executes on the plurality of processor cores in parallel using the portion of the cache as the memory. 
     
     
         20 . The system of  claim 16 , wherein the boot sequence comprises:
 a first boot event of a bootstrap processor (BSP) for handling one or more of a reset vector, processor mode switching, console enabling, creating bootloader memory layout, or chipset initialization;   a second boot event of one of the plurality of processor cores for filling first configuration parameters to initialize the dynamic memory; and   a third boot event of another of the plurality of processor cores for filling second configuration parameter to initialize hardware blocks.