On-Chip Heater

Abstract

An on-chip heater in a concentric rings configuration having non-uniform spacing between heating elements provides improved radial temperature uniformity and low power consumption compared to circular or square heating elements. On-chip heaters are suitable for integration and use with on-chip sensors that require tight temperature control.

What is claimed is: 
     
         1 . A method, comprising:
 depositing a dielectric layer on a first surface of a semiconductor layer;   forming a primary gate stack in the dielectric layer and on the first surface of the semiconductor layer;   forming a secondary gate stack on a second surface of the semiconductor layer; and   forming a heater, in the dielectric layer, comprising:
 forming ring-shaped heating elements in a concentric arrangement; 
 electrically connecting a first connection point of an innermost heating element to a first connection point of an outermost heating element from the ring-shaped heating elements; 
 electrically connecting a second connection point of the innermost heating element to a first voltage source; and 
 electrically connecting a second connection point of the outermost heating element to a second voltage source different from the first voltage source. 
   
     
     
         2 . The method of  claim 1 , wherein forming the primary gate stack comprises:
 depositing a gate dielectric on the first surface of the semiconductor layer; and   depositing a gate electrode on the gate dielectric.   
     
     
         3 . The method of  claim 1 , wherein forming the secondary gate stack comprises:
 depositing a gate dielectric on the second surface of the semiconductor layer; and   depositing a capture reagent on the gate dielectric.   
     
     
         4 . The method of  claim 1 , wherein the first connection points are at a first end of a quadrant of the ring-shaped heating elements and the second connection points are at a second end of the quadrant of the ring-shaped heating elements. 
     
     
         5 . The method of  claim 1 , further comprising forming a temperature sensor in the semiconductor layer. 
     
     
         6 . The method of  claim 1 , further comprising forming a temperature sensor in the semiconductor layer prior to forming the secondary gate stack. 
     
     
         7 . The method of  claim 1 , wherein forming the heater further comprises electrically connecting a third connection point of the innermost heating element to a third connection point of the outermost heating element; and
 wherein the first and third connection points are in opposite quadrants of the ring-shaped heating elements.   
     
     
         8 . The method of  claim 1 , wherein forming the heater further comprises:
 electrically connecting a fourth connection point of the innermost heating element to the first voltage source;   electrically connecting a fourth connection point of the outermost heating element to the second voltage source; and   wherein the second and fourth connection points are in opposite quadrants of the ring-shaped heating elements.   
     
     
         9 . The method of  claim 1 , wherein electrically connecting the second connection point of the innermost heating element to the first voltage source comprises electrically connecting the second connection point of the innermost heating element to a ground voltage. 
     
     
         10 . The method of  claim 1 , wherein electrically connecting the second connection point of the outermost heating element to the second voltage source comprises electrically connecting the second connection point of the outermost heating element to a supply voltage source. 
     
     
         11 . A method, comprising:
 depositing a dielectric layer on a first surface of a substrate;   forming a first gate on the first surface of the substrate;   forming a second gate on a second surface of the substrate;   forming a multi-level interconnect structure in the dielectric layer; and   forming a heater electrically connected to the multi-level interconnect structure, wherein forming the heater comprises:
 forming a first pair of heating elements in the dielectric layer; and 
 forming a second pair of heating elements between the first pair of heating elements, wherein a sum of the radii of the first pair of heating elements is equal to a sum of the radii of the second pair of heating elements. 
   
     
     
         12 . The method of  claim 11 , wherein forming the heater further comprises forming the first and second pairs of heating elements in a concentric arrangement. 
     
     
         13 . The method of  claim 11 , wherein forming the heater further comprises forming each heating element in the first and second pairs of heating elements with a ring-shaped structure. 
     
     
         14 . The method of  claim 11 , further comprising forming a fluidic channel on the second gate. 
     
     
         15 . The method of  claim 11 , wherein forming the second gate comprises:
 depositing a gate dielectric on the second surface of the substrate; and   depositing a capture reagent on the gate dielectric.   
     
     
         16 . The method of  claim 15 , wherein depositing the capture reagent comprises depositing a biological molecule. 
     
     
         17 . A method, comprising:
 forming a dual gate field effect transistor (FET) on a substrate;   depositing a dielectric layer on the dual gate FET;   forming a multi-level interconnect structure in the dielectric layer; and   forming a heater electrically connected to the multi-level interconnect structure, wherein forming the heater comprises:
 forming a plurality of heating elements in a concentric arrangement; 
 electrically connecting an innermost heating element from the plurality of heating elements to a first voltage source; and 
 electrically connecting an outermost heating element from the plurality of heating elements to a second voltage source different from the first voltage source. 
   
     
     
         18 . The method of  claim 17 , wherein electrically connecting the innermost heating element to the first voltage source comprises electrically connecting the innermost heating element to a ground voltage. 
     
     
         19 . The method of  claim 17 , wherein electrically connecting the outermost heating element to the second voltage source comprises electrically connecting the outermost heating element to a supply voltage source. 
     
     
         20 . The method of  claim 17 , wherein forming the dual gate FET comprises:
 depositing a first gate dielectric on a first surface of the substrate;   depositing a gate electrode on the first gate dielectric;   depositing a second gate dielectric on the second surface of the substrate; and   depositing a capture reagent on the second gate dielectric.