US2023378305A1PendingUtilityA1

Contact structures in semiconductor devices

Assignee: TAIWAN SEMICONDUCTOR MFG CO LTDPriority: Jul 31, 2020Filed: Jul 28, 2023Published: Nov 23, 2023
Est. expiryJul 31, 2040(~14 yrs left)· nominal 20-yr term from priority
H10D 64/0112H10W 20/40H10W 20/035H10W 20/047H10W 20/076H10W 10/17H10W 10/014H10D 30/62H10D 30/024H10D 62/151H10D 84/834H10D 84/013H10D 84/0158H10D 84/0149H10D 84/038H10D 64/647H10D 30/6219H10D 30/6211H10D 64/62H10D 62/83H10D 84/853H10D 84/0186H10D 84/017H10D 84/0193H01L 29/45H01L 21/28518H01L 29/0847H01L 29/41791H01L 29/66795H01L 29/7851H01L 21/823418H01L 29/7839
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Claims

Abstract

A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a gate structure disposed on first and second fin structures;   a merged source/drain (S/D) region disposed on the first and second fin structures; and   a contact structure disposed on the merged S/D region,   wherein the contact structure comprises ternary compound clusters disposed on the merged S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound clusters and the merged S/D region, and a contact plug disposed on the WFM silicide layer.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the ternary compound clusters comprise a zirconium-based ternary compound. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the ternary compound clusters comprise faceted surfaces. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the ternary compound clusters are separated from each other by interfaces between the WFM silicide layer and the S/D region. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising a dipole layer disposed at interfaces between the WFM silicide layer and the S/D region. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising a dipole layer disposed at interfaces between the ternary compound clusters and the S/D region. 
     
     
         7 . A method, comprising:
 forming a fin structure on a substrate;   forming a source/drain (S/D) region on the fin structure;   forming a contact opening on the S/D region;   forming a doped work function metal (WFM) silicide layer within the contact opening;   forming a ternary compound layer between the doped WFM silicide layer and the S/D region; and   forming a contact plug within the contact opening.   
     
     
         8 . The method of  claim 7 , wherein forming the doped WFM silicide layer comprises depositing a dopant source layer on the S/D region, and
 wherein the dopant source layer comprises a metal with an electronegativity value smaller than an electronegativity value of a metal in a metal silicide of the doped WFM silicide layer.   
     
     
         9 . The method of  claim 7 , wherein forming the ternary compound layer comprises:
 depositing a zirconium-based dopant source layer on the S/D region;   depositing a WFM layer on the zirconium-based dopant source layer; and   performing an annealing process.   
     
     
         10 . The method of  claim 7 , wherein forming the ternary compound layer comprises forming a zirconium-based ternary compound layer. 
     
     
         11 . The method of  claim 7 , wherein forming the ternary compound layer comprises forming the ternary compound layer with faceted surfaces facing the doped WFM silicide layer. 
     
     
         12 . The method of  claim 7 , further comprising performing an annealing process after forming the doped WFM silicide layer. 
     
     
         13 . The method of  claim 7 , further comprising depositing a nitride capping layer on the doped WFM silicide layer. 
     
     
         14 . A method, comprising:
 forming a gate structure disposed on a substrate;   forming a source/drain (S/D) region on the substrate; and   forming a contact structure on the S/D region, wherein forming the contact structure comprises:
 depositing a dopant source layer on the S/D region; 
 depositing a metal layer on the dopant source layer; and 
 depositing a contact plug on the metal layer. 
   
     
     
         15 . The method of  claim 14 , wherein depositing the dopant source layer comprises depositing a transition metal layer with an electronegativity value smaller than an electronegativity value of the metal layer. 
     
     
         16 . The method of  claim 14 , wherein depositing the dopant source layer comprises depositing a zirconium-based transition metal layer. 
     
     
         17 . The method of  claim 14 , further comprises performing an annealing process to form a ternary compound layer directly on the S/D region. 
     
     
         18 . The method of  claim 14 , further comprising depositing a barrier layer on the S/D region prior to depositing the dopant source layer. 
     
     
         19 . The method of  claim 14 , further comprising depositing a nitride layer on the metal layer prior to depositing the contact plug. 
     
     
         20 . The method of  claim 14 , further comprising:
 depositing an other metal layer on the metal layer prior to depositing the contact plug; and   performing a nitridation process on the another metal layer.

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