Mask-free process for improving drain to gate breakdown voltage in semiconductor devices

Abstract

A semiconductor device may include a first device on a first portion of a substrate, a second device on a second portion of the substrate, and a third device on a third portion of the substrate. The third device may include an oxide layer that is formed from an oxide layer that is a sacrificial oxide layer for the first device and the second device. The third device may include a gate provided on the oxide layer, a set of spacers provided on opposite sides of the gate, and a source region provided in the third portion of the substrate on one side of the gate. The third device may include a drain region provided in the third portion of the substrate on another side of the gate, and a protective oxide layer provided on a portion of the gate and a portion of the drain region.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate that includes a first portion, a second portion, and a third portion;   a first device on the first portion of the substrate;   a second device on the second portion of the substrate; and   a third device on the third portion of the substrate and comprising:
 an oxide layer on the third portion,
 wherein a thickness of the oxide layer is greater than thicknesses of other oxide layers utilized for the first device and the second device, 
 
 a gate on the oxide layer, 
 a set of spacers on opposite sides of the gate, 
 a source region in the third portion of the substrate on one side of the gate, 
 a drain region in the third portion of the substrate on another side of the gate, and 
 a protective oxide layer on a portion of the gate and a portion of the drain region. 
   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 silicide layers over portions of the gate, the source region, and the drain region.   
     
     
         3 . The semiconductor device of  claim 1 , wherein the protective oxide layer covers a portion of the third portion of the substrate and covers an entire surface of a spacer in the set of spacers. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the third device further comprises:
 silicide layers over portions of the gate, the source region, and the drain region except for the portion of the gate and the portion of the drain region covered by the protective oxide layer.   
     
     
         5 . The semiconductor device of  claim 1 , wherein:
 the first device is a core device,   the second device is an input/output device, and   the third device is a high voltage device.   
     
     
         6 . The semiconductor device of  claim 1 , wherein the third portion of the substrate includes a p-type body region and an n-type drift region,
 wherein the source region is in the p-type body region and the drain region is in the n-type drift region.   
     
     
         7 . The semiconductor device of  claim 1 , wherein the third device is a high voltage device. 
     
     
         8 . A semiconductor device, comprising:
 a substrate that includes a first portion, a second portion, and a third portion;   a first device on the first portion of the substrate and comprising:
 a first oxide layer on the first portion; 
   a second device on the second portion of the substrate and comprising:
 a second oxide layer on the second portion,
 wherein a thickness of the second oxide layer is greater than a thickness of the first oxide layer; and 
 
   a third device on the third portion of the substrate and comprising:
 a third oxide layer on the third portion,
 wherein a thickness of the third oxide layer is greater than the thickness of the second oxide layer, 
 a gate on the third oxide layer, 
 a set of spacers on opposite sides of the gate, 
 a source region in the third portion of the substrate on a first side of the gate, 
 a drain region in the third portion of the substrate on a second side of the gate, and 
 a fourth oxide layer on a portion of the gate and a portion of the drain region. 
 
   
     
     
         9 . The semiconductor device of  claim 8 , further comprising:
 a first silicide layer over another portion of the gate;   a second silicide layer over a portion of the source region; and   a third silicide layer over a portion of the drain region.   
     
     
         10 . The semiconductor device of  claim 8 , wherein the gate is a first gate, the set of spacers is a first set of spacers, the source region is a first source region, and the drain region is a first drain region; and
 wherein the first device further comprises:
 a second gate on the first oxide layer, 
 a second set of spacers on opposite sides of the second gate, 
 a second source region in the first portion of the substrate on a first side of the second gate, and 
 a second drain region in the first portion of the substrate on a second side of the second gate. 
   
     
     
         11 . The semiconductor device of  claim 10 , further comprising:
 a first silicide layer over the second gate;   a second silicide layer a portion of the second source region; and   a third silicide layer over a portion of the second drain region.   
     
     
         12 . The semiconductor device of  claim 8 , wherein the gate is a first gate, the set of spacers is a first set of spacers, the source region is a first source region, and the drain region is a first drain region; and
 wherein the second device further comprises:
 a second gate on the second oxide layer, 
 a second set of spacers on opposite sides of the second gate, 
 a second source region in the second portion of the substrate on a first side of the second gate, and 
 a second drain region in the second portion of the substrate on a second side of the second gate. 
   
     
     
         13 . The semiconductor device of  claim 12 , further comprising:
 a first silicide layer over the second gate;   a second silicide layer a portion of the second source region; and   a third silicide layer over a portion of the second drain region.   
     
     
         14 . The semiconductor device of  claim 8 , wherein:
 the first device is a core device,   the second device is an input/output device, and   the third device is a high voltage device.   
     
     
         15 . A semiconductor device, comprising:
 a substrate that includes a first portion, a second portion, and a third portion;   a first device on the first portion of the substrate and comprising:
 a first oxide layer on the first portion, and 
 a first gate on the first oxide layer; 
   a second device on the second portion of the substrate and comprising:
 a second oxide layer on the second portion,
 wherein a thickness of the second oxide layer is greater than a thickness of the first oxide layer, and 
 
 a second gate on the second oxide layer; and 
   a third device on the third portion of the substrate and comprising:
 a third oxide layer on the third portion,
 wherein a thickness of the third oxide layer is greater than the thickness of the second oxide layer, 
 
 a third gate on the third oxide layer, 
 a first spacer on a first side of the third gate, 
 a second spacer on a second side of the third gate, 
 a source region in the third portion of the substrate on the first side of the third gate, 
 a drain region in the third portion of the substrate on the second side of the third gate, and 
 a fourth oxide layer on a portion of the third gate and a portion of the drain region. 
   
     
     
         16 . The semiconductor device of  claim 15 , wherein the fourth oxide layer is on the second spacer. 
     
     
         17 . The semiconductor device of  claim 15 , further comprising:
 a first silicide layer over another portion of the third gate;   a second silicide layer a portion of the source region; and   a third silicide layer over another portion of the drain region.   
     
     
         18 . The semiconductor device of  claim 15 , wherein the third portion of the substrate includes a p-type body region and an n-type drift region,
 wherein the source region is in the p-type body region and the drain region is in the n-type drift region.   
     
     
         19 . The semiconductor device of  claim 15 , further comprising:
 a first silicide layer over the first gate;   a second silicide layer over the second gate; and   a third silicide layer over a portion of the third gate.   
     
     
         20 . The semiconductor device of  claim 15 , wherein:
 the first device is a core device,   the second device is an input/output device, and   the third device is a high voltage device.