Semiconductor Device and Method of Forming Same

Abstract

In an embodiment, a method of forming a semiconductor device includes: forming a first oxide layer over a semiconductor fin structure; performing a first nitridation process to convert the first oxide layer to an oxynitride layer; depositing a silicon-containing layer over the oxynitride layer; performing a first anneal on the silicon-containing layer, wherein after performing the first anneal, the oxynitride layer has a higher nitrogen atomic concentration at an interface with the semiconductor fin structure than in a bulk region of the oxynitride layer; and forming a dummy gate structure over the silicon-containing layer.

What is claimed is: 
     
         1 . A method of forming a semiconductor device, the method comprising:
 forming a first oxide layer over a semiconductor fin structure;   performing a first nitridation process to convert the first oxide layer to an oxynitride layer;   depositing a silicon-containing layer over the oxynitride layer;   performing a first anneal on the silicon-containing layer, wherein after performing the first anneal, the oxynitride layer has a higher nitrogen atomic concentration at an interface with the semiconductor fin structure than in a bulk region of the oxynitride layer; and   forming a dummy gate structure over the silicon-containing layer.   
     
     
         2 . The method of  claim 1 , wherein the silicon-containing layer further comprises germanium, and wherein after performing the first anneal the oxynitride layer comprises germanium. 
     
     
         3 . The method of  claim 1 , wherein performing the first nitridation process comprises a thermal nitridation performed at temperatures ranging from 700° C. to 1200° C. in an ambient of at least one of NH 3 , NO, N 2 O, and NO 2 . 
     
     
         4 . The method of  claim 1  further comprising:
 etching the semiconductor fin structure to form a first recess, a sidewall of the first recess exposing a semiconductor layer and a sacrificial layer of the semiconductor fin structure; 
 etching the sacrificial layer to form a second recess in the sidewall of the first recess; and 
 performing a second nitridation treatment to form a nitrogen-containing layer in the first recess and in the second recess. 
 
     
     
         5 . The method of  claim 4  further comprising:
 forming a dielectric layer over the nitrogen-containing layer in the first recess and in the second recess; 
 etching the nitrogen-containing layer and the dielectric layer, wherein after the etching the nitrogen-containing layer and the dielectric layer, remaining portions of the dielectric layer form an inner spacer in the second recess; and 
 epitaxially growing a source/drain region in the first recess. 
 
     
     
         6 . The method of  claim 5 , wherein the source/drain region comprises germanium, and wherein after the epitaxially growing the source/drain region, the nitrogen-containing layer comprises germanium. 
     
     
         7 . The method of  claim 6 , wherein the second nitridation treatment comprises a plasma nitridation performed at a temperature of 20° C. to 700° C. using precursors comprising at least one of N 2 , NH 3 , NO, N 2 O, and NO 2 . 
     
     
         8 . A method of forming a semiconductor device, the method comprising:
 forming a fin structure over a substrate, the fin structure comprising a fin and nanostructures disposed over the fin, the nanostructures comprising a sacrificial layer disposed over the fin and a semiconductor layer over the sacrificial layer;   etching a first recess in the fin structure to expose a sidewall of the nanostructures;   forming a nitrogen-containing layer over a sidewall of the semiconductor layer, and a sidewall of the sacrificial layer;   forming a dielectric layer over the nitrogen-containing layer;   etching the dielectric layer and the nitrogen-containing layer to expose the sidewall of the semiconductor layer; and   forming an epitaxial region in the first recess and directly adjacent to the semiconductor layer.   
     
     
         9 . The method of  claim 8  further comprising performing a first anneal on the epitaxial region, wherein after the performing the first anneal, the dielectric layer comprises germanium. 
     
     
         10 . The method of  claim 8  further comprising, prior to forming the nitrogen-containing layer, etching the sacrificial layer to form a second recess in the sidewall of the nano structures, wherein a portion of the nitrogen-containing layer is formed in the second recess, and wherein a portion of the dielectric layer is formed in the second recess. 
     
     
         11 . The method of  claim 8  further comprising:
 removing the sacrificial layer to form a third recess interposed between the substrate and the semiconductor layer, wherein the removing the sacrificial layer comprises etching a portion of the nitrogen-containing layer; and 
 forming a gate electrode in the third recess. 
 
     
     
         12 . The method of  claim 8  further comprising, before etching the first recess:
 forming an additional nitrogen-containing layer over the fin structure; 
 forming a germanium-containing layer over the additional nitrogen-containing layer; and 
 forming a dummy gate structure over the fin structure. 
 
     
     
         13 . The method of  claim 12  further comprising, after forming the germanium-containing layer and before etching the first recess in the fin, performing a second anneal, wherein after performing the second anneal the additional nitrogen-containing layer comprises germanium. 
     
     
         14 . The method of  claim 12  further comprising:
 removing the dummy gate structure; 
 removing the additional nitrogen-containing layer from the fin structure; and 
 forming a replacement gate. 
 
     
     
         15 . A semiconductor device, comprising:
 a gate dielectric and a conductive material disposed between a first nanostructure and a second nanostructure;   a source/drain region physically contacting the first nanostructure and the second nanostructure;   a first nitrogen-containing layer disposed adjacent the first nanostructure;   a second nitrogen-containing layer disposed adjacent the second nanostructure; and   an inner spacer interposed between the gate dielectric and the source/drain region.   
     
     
         16 . The semiconductor device of  claim 15 , wherein the inner spacer is interposed between the first nitrogen-containing layer and the second nitrogen-containing layer. 
     
     
         17 . The semiconductor device of  claim 15 , wherein the first nitrogen-containing layer comprises silicon oxynitride, and wherein the second nitrogen-containing layer comprises silicon oxynitride. 
     
     
         18 . The semiconductor device of  claim 17 , wherein a first portion of the first nitrogen-containing layer at an interface with the first nanostructure has a greater nitrogen concentration than a second portion of the first nitrogen-containing layer distal from the first nanostructure. 
     
     
         19 . The semiconductor device of  claim 18 , wherein the second portion of the first nitrogen-containing layer further comprises germanium. 
     
     
         20 . The semiconductor device of  claim 15 , wherein the inner spacer comprises germanium.