Methods for forming image sensors
Abstract
Various embodiments of the present disclosure are directed towards methods for forming an image sensor in which a device layer overlies and has a different semiconductor material than a substrate and in which the device layer has high crystalline quality. Some embodiments of the methods include: epitaxially growing the device layer on the substrate; patterning the device layer to form a trench dividing the device layer into mesa structures corresponding to pixels; forming an inter-pixel dielectric layer filling the trench and separating the mesa structures; and forming photodetectors in the mesa structures. Other embodiments of the methods include: depositing the inter-pixel dielectric layer over the substrate; patterning the inter-pixel dielectric layer to form cavities corresponding to the pixels; epitaxially growing the mesa structures in the cavities; and forming the photodetectors in the mesa structures.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . An image sensor, comprising:
a device layer overlying and recessed into a substrate; a cap layer overlying the device layer; a photodetector in the device layer; and an interlayer cupping an underside of the device layer and separating the device layer from the substrate; wherein the substrate, the cap layer, the interlayer, and the device layer are semiconductors, wherein the interlayer is undoped, and wherein the device layer has a different energy bandgap than the substrate, the cap layer, and the interlayer.
2 . The image sensor according to claim 1 , further comprising:
a dielectric layer localized on and directly contacting a top surface of the interlayer.
3 . The image sensor according to claim 2 , wherein the dielectric layer extends laterally in a closed path along a boundary of the device layer.
4 . The image sensor according to claim 2 , wherein a top layout of the device layer has an X dimension and a Y dimension that are orthogonal to each other, and wherein a width of the dielectric layer is about 0.1% to about 1% of an average of the X and Y dimensions.
5 . The image sensor according to claim 1 , wherein the cap layer is localized over the device layer.
6 . The image sensor according to claim 1 , wherein the cap layer overlies the substrate at locations laterally offset from the device layer and the interlayer.
7 . The image sensor according to claim 1 , wherein the cap layer has substantially the same energy band gap as the substrate.
8 . The image sensor according to claim 1 , wherein a top surface of the device layer is elevated relative to a top surface of the substrate.
9 . The image sensor according to claim 1 , wherein a top surface of the device layer is recessed relative to a top surface of the substrate.
10 . The image sensor according to claim 1 , wherein the device layer extends into the substrate to a depth, and wherein a vertical offset between a top surface of the device layer and a top surface of the substrate is within about 10% of the depth.
11 . An image sensor, comprising:
a device layer recessed into a top of a substrate; a photodetector in the device layer; an interlayer extending along a sidewall of the device layer and a bottom surface of the device layer, wherein the interlayer separates the device layer from the substrate; and an interlayer cap localized on and directly contacting a top surface of the interlayer, wherein the interlayer cap is dielectric; wherein the substrate and the interlayer are a first semiconductor type, wherein the device layer is a second semiconductor type different than the first semiconductor type, and wherein the interlayer is undoped.
12 . The image sensor according to claim 11 , wherein a width of the interlayer cap is a same as a thickness of the interlayer.
13 . The image sensor according to claim 11 , wherein the interlayer cap has a bottom surface recessed relative to a top surface of the substrate and further has a top surface elevated relative to the top surface of the substrate.
14 . The image sensor according to claim 11 , further comprising:
a device cap layer overlying and directly contacting the device layer, wherein the device cap layer is the first semiconductor type.
15 . The image sensor according to claim 14 , wherein the interlayer cap comprises a pair of segments between which the device cap layer is arranged, and wherein the segments have individual top surfaces recessed relative to a top surface of the device cap layer.
16 . An image sensor, comprising:
a germanium device layer recessed into a top of a silicon substrate; a photodetector in the germanium device layer; an intrinsic silicon layer cupping an underside of the germanium device layer and separating the germanium device layer from the silicon substrate; and a silicon oxide cap overlying and directly contacting a top surface of the intrinsic silicon layer, wherein the silicon oxide cap has a ring-shaped top geometry.
17 . The image sensor according to claim 16 , further comprising:
a silicon cap layer covering the germanium device layer, wherein the silicon cap layer and the germanium device layer have substantially the same width.
18 . The image sensor according to claim 16 , wherein the silicon oxide cap has a sidewall facing and directly contacting the germanium device layer, wherein a top edge of the sidewall is elevated relative to a top surface of the germanium device layer, and wherein a bottom edge of the sidewall is recessed relative to the top surface of the germanium device layer.
19 . The image sensor according to claim 18 , wherein the top edge of the sidewall is elevated relative to a top surface of the silicon substrate, and wherein the bottom edge of the sidewall is recessed relative to the top surface of the silicon substrate.
20 . The image sensor according to claim 16 , further comprising:
a doped implant isolation region extending vertically into the silicon substrate from the top of the silicon substrate, and further extending laterally around the germanium device layer, and wherein the doped implant isolation region is spaced from the intrinsic silicon layer and the germanium device layer.Join the waitlist — get patent alerts
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